US4377728A
Expired / Lapsed
US
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Phase locked loop with improved lock-in
Assignee: Motorola Solutions Inc
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Filing: 1981-03-04
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Granted: 1983-03-22
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Expires: 2001-03-04
Abstract
Abstract The circuit determines whether an incoming frequency is within the normal "lock-in" range of a phase locked loop VCO or not, and whether it is higher or lower than the VCO frequency. If not within normal range, the beats are rectified and gated to provide a DC control voltage of the proper value and polarity for locking the oscillator on the incoming frequency. Rectification may be half or full wave as needed, and the circuit may include filter bandwidth control as well. This circuit is suitable for signals of any waveform, quadrature signals, and AM stereophonic signals.
Inventors
- 👤 Francis H. Hilbert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:53
CPC Classifications
H; H04; H04H; H04H20/00; H04H20/44; H04H20/46; H04H20/47; H04H20/49; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/10; H03L7/085; H03L7/087; H03L7/107; H03L7/1075; H03L7/113
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
126 words
A phase locked loop comprising: input means; first, in-phase detector means coupled to the input means; second, quadrature detector means coupled to the input means; filter means coupled to the second detector means output; oscillator means coupled to be controlled by the filter means output, for providing two output signals in quadrature to the first and second detector means respectively; logic means coupled to the outputs of the first and second detector means for detecting beats between said output signals, for detecting the relative phase of said signals, and for providing a control signal in response to said detection; and gating means coupled to control the connection between the second detector means and the filter means in response to the control signal from the logic means.
Claim 2
Dependent Claim
126 words
A phase locked loop comprising: input means; first, in-phase detector means coupled to the input means; second, quadrature detector means coupled to the input means; filter means coupled to the second detector means output; oscillator means coupled to be controlled by the filter means output, for providing two output signals in quadrature to the first and second detector means respectively; logic means coupled to the outputs of the first and second detector means for detecting beats between said output signals, for detecting the relative phase of said signals, and for providing a control signal in response to said detection; and gating means coupled to control the connection between the second detector means and the filter means in response to the control signal from the logic means.
Claim 3
Dependent Claim
18 words
A phase locked loop in accordance with claim 1 and wherein the filter means is a low-pass filter.
Claim 4
Dependent Claim
66 words
A phase locked loop in accordance with claim 1 and wherein the logic means includes third detector means for detecting the zero crossings of the second detector means output signal, steering means and bistable means, the steering means coupled to steer the third detector means output signal to the respective inputs of the bistable means in response to the output signal of the first detector means.
Claim 5
Dependent Claim
96 words
A phase locked loop in accordance with claim 1 wherein the logic means further includes a current source, first transistor means coupled to the second detector means for providing a first signal in response to the zero crossings of said detector means output signal, bistable means coupled to control the gating means, second transistor means coupled to the first transistor means, to the first detector means and to the bistable means for coupling said first signal to ones of the bistable means inputs in response to the instantaneous polarity of the first detector means output signal.
Claim 6
Dependent Claim
37 words
A phase locked loop in accordance with claim 1 wherein the gating means includes means for providing half-wave rectification of the signals from the second, quadrature detector in response to the control signal from the logic means.
Claim 7
Dependent Claim
38 words
A phase locked loop in accordance with claim 1 wherein the gating means includes means for providing full wave rectification of the signals from the second, quadrature detector in response to the control signal from the logic means.
Claim 8
Dependent Claim
45 words
A phase locked loop in accordance with claim 1 and further including filter bandwidth control means coupled to the output of one of the detector means and to the filter means for controlling the filter bandwidth in response to the first detector means output signal.
Claim 9
Dependent Claim
22 words
A phase locked loop in accordance with claim 7 wherein said one of the detector means is the first, in-phase detector means.
Claim 10
Dependent Claim
36 words
A phase locked loop in accordance with claim 1 wherein the first and second detector means are coupled to receive AM stereophonic signals and to provide output signals for use in decoding of the stereophonic signals.
Claim 11
Dependent Claim
163 words
A receiver for receiving AM stereophonic signals and comprising: input means; first, in-phase detector means coupled to the input means; second, quadrature detector means coupled to the input means; oscillator means coupled to provide two output signals in quadrature to the first and second detector means respectively; filter means coupled to the second detector means output and coupled to the oscillator means input; logic means coupled to the output of the first and second detector means for detecting beats between the output signals thereof, for detecting the relative phase of said output signals, and for providing a control signal in response to such detection; gating means coupled to control the connection between the second detector means and the filter means in response to the control signal from the logic means; correcting means coupled to correct the input signals of the first and second detector means; and means coupled to the correcting means and to the detector means for deriving the original stereo signals.
Claim 12
Dependent Claim
163 words
A receiver for receiving AM stereophonic signals and comprising: input means; first, in-phase detector means coupled to the input means; second, quadrature detector means coupled to the input means; oscillator means coupled to provide two output signals in quadrature to the first and second detector means respectively; filter means coupled to the second detector means output and coupled to the oscillator means input; logic means coupled to the output of the first and second detector means for detecting beats between the output signals thereof, for detecting the relative phase of said output signals, and for providing a control signal in response to such detection; gating means coupled to control the connection between the second detector means and the filter means in response to the control signal from the logic means; correcting means coupled to correct the input signals of the first and second detector means; and means coupled to the correcting means and to the detector means for deriving the original stereo signals.
Claim 13
Dependent Claim
64 words
A receiver in accordance with claim 10 wherein the correcting means includes third detector means for detecting the envelope modulation on the received signal, comparator means coupled to compare the output signals from the first and third detector means, circuit means coupled for correcting the input signals of the first and second detector means in response to the output signal of the comparator means.
Claim 14
Dependent Claim
19 words
A receiver in accordance with claim 10 wherein the means for deriving the original stereo signals includes matrixing means.
References Cited (Backward Citations)
US3610954A
Cited
US3909735A
Cited
US4057762A
Cited
US4117410A
Cited
US4213096A
Cited
US4253180A
Cited
US4270221A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-03-21 | 1986-09-20 | 1987-03-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-03-21 | 1990-09-20 | 1991-03-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-03-21 | 1994-09-20 | 1995-03-22 | $7700.00 | Window Closed / Lapsed |