Patent US1606359A successfully refreshed from Google Patents.
Patent US4376958A successfully refreshed from Google Patents.
US4376958A
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Modified frequency modulation
Assignee: Elcomatic Ltd
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Filing: 1980-07-08
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Granted: 1983-03-15
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Expires: 2000-07-08
Abstract
Abstract There is described methods and circuitry for decoding modified frequency modulated (MFM) information signals as obtained from rotating magnetic storage devices, such as floppy disks and hard disks used in computers. The novel technique involves twice squaring an information carrying data signal mathematically and without saturation, deriving a clock signal from the twice squared data signal using a phase lock loop and thereafter recovering an information signal from said data signal and clock signal.
Inventors
- 👤 Archibald M. Pettigrew
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:29
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1423
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
84 words
A method of decoding MFM information comprising the steps of deriving an information-carrying data signal from a recording medium, mathematically squaring without saturation said data signal to provide a squared data signal, mathematically squaring without saturation said squared data signal, passing said twice squared data signal to a phase lock loop to derive a coherent clock signal, halving the frequency of said coherent clock signal, multiplying the half frequency clock signal with said data signal, and recovering an information signal from said multiplied signal.
Claim 2
Independent Claim
84 words
A method of decoding MFM information comprising the steps of deriving an information-carrying data signal from a recording medium, mathematically squaring without saturation said data signal to provide a squared data signal, mathematically squaring without saturation said squared data signal, passing said twice squared data signal to a phase lock loop to derive a coherent clock signal, halving the frequency of said coherent clock signal, multiplying the half frequency clock signal with said data signal, and recovering an information signal from said multiplied signal.
Claim 3
Dependent Claim
25 words
A method as claimed in claim 1, wherein said data signal is converted to a data pulse train before being multiplied with said half frequency.
Claim 4
Dependent Claim
29 words
A method as claimed in claim 2, wherein the pulses of said data pulse train have a period equal to one half of the period of said clock signal.
Claim 5
Independent Claim
27 words
A method as claimed in any preceding claim and further including the step of delaying said data signal prior to multiplication with said half frequency clock signal.
Claim 6
Dependent Claim
26 words
A method as claimed in claim 4, wherein the data signal is delayed by an amount equal to the phase delay of the phase lock loop.
Claim 7
Dependent Claim
18 words
A method as claimed in claim 4, wherein the delay is proportional to the phase lock loop frequency.
Claim 8
Dependent Claim
17 words
A method as claimed in claim 1, wherein said information signal is recovered using D-type latch circuits.
Claim 9
Dependent Claim
25 words
A method as claimed in claim 1, wherein said data signal is mathematically squared without saturation before being multiplied with said half frequency clock signal.
Claim 10
Dependent Claim
17 words
A method as claimed in claim 8, wherein said information signal is recovered using an integrator-correlator-dumper circuit.
Claim 11
Dependent Claim
21 words
A method as claimed in claim 1, wherein the signal is filtered after each squaring step to remove any DC term.
Claim 12
Dependent Claim
105 words
A circuit for decoding MFM information, said circuit including means for deriving an information-carrying data signal from a recording medium, first squaring means for receiving said data signal and mathematically squaring without saturation said data signal to provide a squared data signal, second squaring means for receiving and mathematically squaring without saturation said squared data signal, a phase lock loop for deriving a coherent clock signal from said twice squared data signal, means for halving the frequency of said coherent clock signal, means for multiplying the half frequency clock signal with said data signal, and means for recovering an information signal from said multiplied signal.
Claim 13
Dependent Claim
105 words
A circuit for decoding MFM information, said circuit including means for deriving an information-carrying data signal from a recording medium, first squaring means for receiving said data signal and mathematically squaring without saturation said data signal to provide a squared data signal, second squaring means for receiving and mathematically squaring without saturation said squared data signal, a phase lock loop for deriving a coherent clock signal from said twice squared data signal, means for halving the frequency of said coherent clock signal, means for multiplying the half frequency clock signal with said data signal, and means for recovering an information signal from said multiplied signal.
Claim 14
Dependent Claim
31 words
A circuit as claimed in claim 11, including means for generating a data pulse train from said data signal, said data pulse train being multiplied with said half frequency clock signal.
Claim 15
Dependent Claim
24 words
A circuit as claimed in claim 12, wherein said means for generating said data pulse train includes a zero-crossing detector and a monostable circuit.
Claim 16
Dependent Claim
26 words
A circuit as claimed in claim 13, wherein the monostable circuit has a variable period which is proportional to the frequency of the phase lock loop.
Claim 17
Dependent Claim
18 words
A circuit as claimed in claim 11, wherein said means for recovering said information signal includes D-latch circuits.
Claim 18
Dependent Claim
25 words
A circuit as claimed in claim 11, wherein said data signal is mathematically squared without saturation before being multiplied with said half frequency clock signal.
Claim 19
Dependent Claim
19 words
A circuit as claimed in claim 16, wherein said means for recovering an information signal includes an integrator-correlator-dumper circuit.
Claim 20
Dependent Claim
97 words
A circuit for decoding MFM information, said circuit including means for deriving an information-carrying data signal from a recording medium, a monostable circuit for receiving said data signal and generating a data pulse train from said data signal, a bandpass filter for filtering said data pulse train, a phase lock loop for deriving a coherent clock signal from said filtered data pulse train, means for halving the frequency of said coherent clock signal, a multiplier for multiplying the half frequency clock signal with the data signal, and means for recovering an information signal from said multiplied signal.
Claim 21
Dependent Claim
97 words
A circuit for decoding MFM information, said circuit including means for deriving an information-carrying data signal from a recording medium, a monostable circuit for receiving said data signal and generating a data pulse train from said data signal, a bandpass filter for filtering said data pulse train, a phase lock loop for deriving a coherent clock signal from said filtered data pulse train, means for halving the frequency of said coherent clock signal, a multiplier for multiplying the half frequency clock signal with the data signal, and means for recovering an information signal from said multiplied signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-03-14 | 1986-09-13 | 1987-03-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-03-14 | 1990-09-13 | 1991-03-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-03-14 | 1994-09-13 | 1995-03-15 | $7700.00 | Window Closed / Lapsed |