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US4376275A
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Very fast BCD-to-binary converter
Assignee: Unisys Corp
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Filing: 1981-04-03
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Granted: 1983-03-08
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Expires: 2001-04-03
Abstract
Abstract A very fast BCD-to-binary converter useful for addressing a digital memory. The converter includes a logical level comprised of at least three specially chosen AND-OR-INVERT integrated circuit gates, having at least five inputs, for producing binary output signals representing bits of the converted binary number.
Inventors
- 👤 Laurence P. Flora
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 14:17
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/02; H03M7/12
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
180 words
In apparatus for converting a plurality of BCD binary signals representing a plurality of BCD digits into a plurality of binary signals representing an output binary number, the combination comprising: a plurality of at least three AND-OR-INVERT gates provided at the same logical level, each AND-OR-INVERT gate having the following characteristics: (1) the gate is provided on a single integrated circuit chip; (2) the gate has an input capability of at least five input signals; (3) the gate is capable of ORing at least two different logical functions of the inputs; (4) at least one of the ORed functions includes an AND combination of at least two inputs; (5) the gate output corresponds to the INVERTed ORed result; and (6) the gate provides a worst-case delay of no greater than 7 nanoseconds; logic means responsive to particular ones of said BCD binary signals for applying a predetermined plurality of binary signals to each of said AND-OR-INVERT gates such that each AND-OR-INVERT gate provides a binary output signal corresponding to a different one of the binary signals representing said binary number.
Claim 2
Dependent Claim
180 words
In apparatus for converting a plurality of BCD binary signals representing a plurality of BCD digits into a plurality of binary signals representing an output binary number, the combination comprising: a plurality of at least three AND-OR-INVERT gates provided at the same logical level, each AND-OR-INVERT gate having the following characteristics: (1) the gate is provided on a single integrated circuit chip; (2) the gate has an input capability of at least five input signals; (3) the gate is capable of ORing at least two different logical functions of the inputs; (4) at least one of the ORed functions includes an AND combination of at least two inputs; (5) the gate output corresponds to the INVERTed ORed result; and (6) the gate provides a worst-case delay of no greater than 7 nanoseconds; logic means responsive to particular ones of said BCD binary signals for applying a predetermined plurality of binary signals to each of said AND-OR-INVERT gates such that each AND-OR-INVERT gate provides a binary output signal corresponding to a different one of the binary signals representing said binary number.
Claim 3
Dependent Claim
35 words
The invention in accordance with claim 1, wherein the BCD binary signals corresponding to the least significant BCD binary signals of said BCD digits are directly employed as binary signals of said output binary number.
Claim 4
Dependent Claim
34 words
The invention in accordance with claim 2, including a digital memory to which the binary signal outputs of said AND-OR-INVERT gates along with the directly provided binary signals are applied as address binary signals.
Claim 5
Dependent Claim
49 words
The invention in accordance with claim 1, wherein at least one AND-OR-INVERT gate has less than five inputs applied thereto, and wherein each unused input has a "1" or "0" binary signal applied thereto as determined by the particular function performed on the inputs by the respective AND-OR-INVERT gate.
Claim 6
Dependent Claim
17 words
The invention in accordance with claim 2, wherein said logic means comprises a single level of logic.
Claim 7
Dependent Claim
21 words
The invention in accordance with claim 5, wherein said logic means operates to invert particular ones of said BCD binary signals.
Claim 8
Dependent Claim
18 words
The invention in accordance with claim 6, wherein said single level of logic comprises a plurality of inverters.
Claim 9
Dependent Claim
44 words
The invention in accordance with claim 1, 2, 3, 4, 5, 6 or 7, wherein said apparatus comprises only two logical levels, wherein said logic means is one logical level, and wherein the logical level including said AND-OR-INVERT gates is the other logical level.
Claim 10
Dependent Claim
31 words
The invention in accordance with claim 8, wherein the logical level including said AND-OR-INVERT gates includes a NOR gate which receives a particular plurality of binary signals from said logic means.
Claim 11
Dependent Claim
38 words
The invention in accordance with claim 9, wherein three BCD digits are applied to said apparatus, wherein said one logical level comprises three inverters, and wherein said other logical level comprises six AND-OR-INVERT gates and one NOR gate.
Claim 12
Dependent Claim
30 words
The invention in accordance with claim 8, wherein at least three BCD digits are applied to said apparatus, and wherein said other logical level comprises at least six AND-OR-INVERT gates.
References Cited (Backward Citations)
US3163859A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-03-07 | 1986-09-06 | 1987-03-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-03-07 | 1990-09-06 | 1991-03-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-03-07 | 1994-09-06 | 1995-03-08 | $7700.00 | Window Closed / Lapsed |