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US4375635A
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US
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Signal measurement apparatus
Assignee: Micron Technology Inc
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Filing: 1980-05-12
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Granted: 1983-03-01
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Expires: 2000-05-12
Abstract
Abstract A word recognizer probe to be removably incorporated with the mainframe of a logic analyzer is disclosed. The use of serial input-parallel output type memory means in the probe minimizes the number of interconnection signal paths between the probe and the mainframe regardless of the input bits to be recognized.
Inventors
- 👤 Chon H. Leow
- 👤 Toshihisa Nagai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 21:35
CPC Classifications
G; G01; G01R; G01R29/00
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
173 words
A signal measurement apparatus for measuring an input signal in response to a selected logic combination of n-channel parallel logic input signals, comprising: a mainframe for receiving said input signal to be measured, said mainframe including a clock generator for generating a clock signal and means for generating a single serial logic signal consisting of n bits in synchronism with said clock signal to set said logic combination; and a subframe including serial input-parallel output type logic memory means and comparison means; said memory means receiving said clock signal and said serial logic signal from said mainframe for converting said serial logic signal into an n-bit parallel logic signal; said comparison means comparing said n-bit parallel logic signal from said memory means with said n-channel parallel logic input signals and generating an output signal when a combination of said n-channel parallel logic input signals corresponds to said logic combination set by said mainframe; wherein said output signal from said comparison means is supplied to said mainframe for controlling the operation of said mainframe.
Claim 2
Dependent Claim
173 words
A signal measurement apparatus for measuring an input signal in response to a selected logic combination of n-channel parallel logic input signals, comprising: a mainframe for receiving said input signal to be measured, said mainframe including a clock generator for generating a clock signal and means for generating a single serial logic signal consisting of n bits in synchronism with said clock signal to set said logic combination; and a subframe including serial input-parallel output type logic memory means and comparison means; said memory means receiving said clock signal and said serial logic signal from said mainframe for converting said serial logic signal into an n-bit parallel logic signal; said comparison means comparing said n-bit parallel logic signal from said memory means with said n-channel parallel logic input signals and generating an output signal when a combination of said n-channel parallel logic input signals corresponds to said logic combination set by said mainframe; wherein said output signal from said comparison means is supplied to said mainframe for controlling the operation of said mainframe.
Claim 3
Dependent Claim
20 words
A signal measurement apparatus according to claim 1, wherein said mainframe is a logic analyzer for measuring logic input signal(s).
Claim 4
Dependent Claim
28 words
A signal measurement apparatus according to claim 1, wherein said subframe is a word recognizer controlled by said mainframe and supplying a detected output signal to said mainframe.
Claim 5
Dependent Claim
37 words
A signal measurement apparatus according to claim 3, wherein said mainframe further includes a second word recognizer for generating an output signal when said logic input signals applied to said mainframe correspond to a preselected logic combination.
Claim 6
Dependent Claim
28 words
A signal measurement apparatus according to claim 4, wherein said mainframe further including logic means generating an output when both of said word recognizers generate said output signals.
Claim 7
Dependent Claim
20 words
A signal measurement apparatus according to claim 1, wherein said serial input-parallel output type logic memory is a shift register.
Claim 8
Dependent Claim
16 words
A signal measurement apparatus according to claim 1, wherein said comparison means consists of logic gates.
Claim 9
Dependent Claim
24 words
A signal measurement apparatus according to claim 1, wherein said means for generating said serial logic signal consists of a keyboard and a processor.
Claim 10
Dependent Claim
39 words
A signal measurement apparatus according to claim 1, wherein said subframe further includes "don't care" means connected to said comparison means for selectively eliminating one or more of said n-channel logic input signals from comparison with said logic combination.
Claim 11
Dependent Claim
157 words
A logic analyzer for measuring one or more logic input signals in response to a selected logic combination of n-channel parallel logic input signals, comprising: a mainframe for receiving said logic input signals to be measured, said mainframe including a clock generator for generating a clock signal and setting means for generating a single serial logic signal consisting of n bits in synchronism with said clock signal to set said logic combination; a word recognizer including serial input-parallel output type logic memory for converting said serial logic signal into an n-bit parallel logic signal and comparison means for generating an output when a combination of said n-channel parallel logic input signals corresponds to a combination of said parallel logic signal from said memory means; and interconnection means for connecting said word recognizer to said mainframe; said interconnection means including conductors for supplying power voltage, reference level, said serial logic signal, said clock signal, and said output signal.
Claim 12
Dependent Claim
157 words
A logic analyzer for measuring one or more logic input signals in response to a selected logic combination of n-channel parallel logic input signals, comprising: a mainframe for receiving said logic input signals to be measured, said mainframe including a clock generator for generating a clock signal and setting means for generating a single serial logic signal consisting of n bits in synchronism with said clock signal to set said logic combination; a word recognizer including serial input-parallel output type logic memory for converting said serial logic signal into an n-bit parallel logic signal and comparison means for generating an output when a combination of said n-channel parallel logic input signals corresponds to a combination of said parallel logic signal from said memory means; and interconnection means for connecting said word recognizer to said mainframe; said interconnection means including conductors for supplying power voltage, reference level, said serial logic signal, said clock signal, and said output signal.
Claim 13
Dependent Claim
27 words
A logic analyzer according to claim 10, wherein said serial input-parallel output type logic memory is a shift register, and said comparison means consists of logic gates.
Claim 14
Dependent Claim
16 words
A logic analyzer according to claim 10, wherein said mainframe includes a keyboard and a processor.
Claim 15
Dependent Claim
39 words
A logic analyzer according to claim 10, wherein said word recognizer further includes "don't care" means connected to said comparison means for selectively eliminating one or more of said n-channel logic input signals from comparison with said logic combination.
Claim 16
Dependent Claim
36 words
A logic analyzer according to claim 10, wherein said mainframe further includes a second word recognizer for generating an output signal when said logic input signals applied to said mainframe correspond to the preselected logic combination.
Claim 17
Dependent Claim
28 words
A logic analyzer according to claim 14, wherein said mainframe further includes logic means for generating an output when both of said word recognizers generate said output signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-02-28 | 1986-08-30 | 1987-03-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-02-28 | 1990-08-30 | 1991-03-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-02-28 | 1994-08-30 | 1995-03-01 | $7700.00 | Window Closed / Lapsed |