Patent JPS6245232A successfully refreshed from Google Patents.
US4375013A
Expired / Lapsed
US
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Device for digit rate reduction of PCM-signals
Assignee: Societe Anonyme de Telecommunications SAT
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Filing: 1980-07-23
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Granted: 1983-02-22
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Expires: 2000-07-23
Abstract
Abstract A digit rate reducing system for PCM signals comprises a predictor stage, an automatic gain control stage, and a quantizer stage for adaptive quantizing. The predictor stage includes a predictor and a subtractor for subtracting from a sample x n of the PCM input signal a predicted signal x pn derived from preceding samples. The subtractor provides a difference signal d n representing prediction error to the automatic gain control (AGC) stage. A divider in the AGC stage divides the difference signal d n by m, providing a divided signal e n to the quantizer stage. In this last stage, a quantizer encodes the divided signal e n into a signal Y n of reduced rate. The predictor uses a first adder which receives the predicted signal x pn and a reconstituted signal d n derived from the reduced rate signal Y n ; a plurality of shift registers and associated multipliers; and a second adder connected to the outputs of the multiplier. Shift registers T 1 . . . T N are coupled to the output of the first adder, and provide a series of delayed signals to multipliers M 1 . . . M N for multiplying by respective coefficients a i (n) derived from the preceding samples. At least one of the predictor coefficients a i (n) is applied to the quantizer, whereby the type of coding is adapted to the statistical properties (ie, the conditional probability distribution curve) of the PCM input signal.
Inventors
- 👤 Denis Cointot
- 👤 Patrice Langlois
- 👤 Guy de Passoz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 07:08
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/04; H03M3/042
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
443 words
A digit rate reducing system for an input PCM signal S, said signal S including a plurality of samples x n having a period T, comprising a predictor stage, an automatic gain compression AGC stage, and a quantizer stage in cascade arrangement; said predictor stage comprising predictor means for deriving a predicted signal x pn from a plurality of preceding samples x n , and subtractor means for substracting from an input signal x n said predicted signal x pn , to form a difference signal d n representing prediction error; said automatic gain compression AGC stage comprising divider means for dividing the amplitude of said difference signal d n to form a divided signal e n ; said quantizer stage comprising first quantizing means for encoding said divided signal e n to form a signal Y n of reduced rate relative to said signal S, and second quantizing means responsive to said signal Y n for providing a decoded signal e n ; said automatic gain compression AGC stage further comprising means responsive to said decoded signal e n for forming a decoded difference signal d n in accordance with said signal Y n ; said predictor stage further comprising first adder means coupled to receive said predicted signal x pn and said decoded difference signal d n , and having an output signal, means for deriving from said plurality of preceding samples x n a plurality of coefficients a i (n), where 1≦i≦N, according to a predetermined algorithm, a plurality of multiplier means M 1 . . . M N coupled to receive the output signal from said first adder, delay line means T 1 . . . T N coupled between said first adder means and said respective multiplier means M 1 . . . M N , said delay line means T 1 . . . T N providing respective delays of kT where 1≦k≦N, said plurality of multiplier means M 1 . . . M N receiving said plurality of coefficients a i (n) respectively and having respective outputs, second adder means coupled to receive said outputs of said plurality of multiplier means M 1 . . . M N and having an output for providing said signal x pn predicted from said plurality of preceding samples x n ; and means respective to said plurality of coefficients a i (n) for comparing at least one of said coefficients a i (n) with a predetermined value to determine the statistical properties of said signal S, said comparing means being coupled to said quantizer stage for adapting the type of encoding to said statistical properties of said signal S.
Claim 2
Dependent Claim
443 words
A digit rate reducing system for an input PCM signal S, said signal S including a plurality of samples x n having a period T, comprising a predictor stage, an automatic gain compression AGC stage, and a quantizer stage in cascade arrangement; said predictor stage comprising predictor means for deriving a predicted signal x pn from a plurality of preceding samples x n , and subtractor means for substracting from an input signal x n said predicted signal x pn , to form a difference signal d n representing prediction error; said automatic gain compression AGC stage comprising divider means for dividing the amplitude of said difference signal d n to form a divided signal e n ; said quantizer stage comprising first quantizing means for encoding said divided signal e n to form a signal Y n of reduced rate relative to said signal S, and second quantizing means responsive to said signal Y n for providing a decoded signal e n ; said automatic gain compression AGC stage further comprising means responsive to said decoded signal e n for forming a decoded difference signal d n in accordance with said signal Y n ; said predictor stage further comprising first adder means coupled to receive said predicted signal x pn and said decoded difference signal d n , and having an output signal, means for deriving from said plurality of preceding samples x n a plurality of coefficients a i (n), where 1≦i≦N, according to a predetermined algorithm, a plurality of multiplier means M 1 . . . M N coupled to receive the output signal from said first adder, delay line means T 1 . . . T N coupled between said first adder means and said respective multiplier means M 1 . . . M N , said delay line means T 1 . . . T N providing respective delays of kT where 1≦k≦N, said plurality of multiplier means M 1 . . . M N receiving said plurality of coefficients a i (n) respectively and having respective outputs, second adder means coupled to receive said outputs of said plurality of multiplier means M 1 . . . M N and having an output for providing said signal x pn predicted from said plurality of preceding samples x n ; and means respective to said plurality of coefficients a i (n) for comparing at least one of said coefficients a i (n) with a predetermined value to determine the statistical properties of said signal S, said comparing means being coupled to said quantizer stage for adapting the type of encoding to said statistical properties of said signal S.
Claim 3
Dependent Claim
213 words
A digit rate reducing system as claimed in claim 1, wherein said means for deriving said plurality of coefficients a i (n) further comprise N circuits, where 1≦i≦N, the i th circuit comprising: first multiplying means for multiplying said decoded difference signal d n by a constant α, and having an output, second multiplying means having two inputs and an output, one of said inputs coupled to the output of said first multiplying means, the second of said inputs coupled to receive the output of delay line means T i ; first adding means for adding the output of said second multiplying means and a coefficient a i (n-1) derived during the preceding period, and having an output; third multiplying means for multiplying the output of said first adding means by a constant (1-β), and having an output; comparator means for selecting a coefficient a oi (n-1) during the preceding period in accordance with the statistical properties of said signal S, and comprising fourth multiplying means for multiplying said coefficient a oi (n-1) by a constant β, and having an output; and second adding means for adding the output of said third multiplying means and the output of said fourth multiplying means, and having an output for providing said coefficient a i (n).
Claim 4
Dependent Claim
76 words
A digit rate reducing system as claimed in claim 2, further comprising comparator means for receiving said coefficient a i (n) from the output of said second adding means, and for comparing said coefficient a i (n) to values corresponding to a limited domain, and for providing an output signal a i * (n) corresponding to the closest value on the limit of the domain if the coefficient a i (n) is outside said limited domain.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-02-21 | 1986-08-23 | 1987-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-02-21 | 1990-08-23 | 1991-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-02-21 | 1994-08-23 | 1995-02-22 | $7700.00 | Window Closed / Lapsed |