Patent US4374915A successfully refreshed from Google Patents.
US4374915A
Expired / Lapsed
US
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High contrast alignment marker for integrated circuit fabrication
Assignee: Intel Corp
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Filing: 1981-07-30
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Granted: 1983-02-22
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Expires: 2001-07-30
Abstract
Abstract A wafer marker is described for aligning masks with the wafer. The marker comprises a depression in the wafer which is defined by sloped sides and a pitted bottom. The sloped sides and pitted bottom do not directly reflect light as does the surface of the surrounding silicon and thus the marker appears as a darker region. The bottom of the depression is pitted by exposing the anode during a silicon plasma etching step.
Inventors
- 👤 C. Norman Ahlquist
- 👤 Yaw Wen Hu
- 👤 Peter F. Schoen
- 👤 Paul A. Poenisch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:49
CPC Classifications
G; G03; G03F; G03F9/00; G03F9/70; G03F9/7073; G03F9/7076
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
124 words
In the fabrication of integrated circuits on a substrate wherein radiation is passed through a masking member to expose certain regions of a photosensitive layer, a process for forming an improved marker for permitting better alignment between said masking member and said substrate, comprising the steps of: forming a photoresist layer on said substrate; forming an opening in said layer at the proposed site of said marker; etching a depression in said substrate in said substrate at said opening, said depression including sloped sides and a generally planer bottom region; roughening said bottom region such that said bottom region directly reflects less radiation than said substrate surface; whereby a high contrast marker for use in aligning said masking member with said substrate is formed.
Claim 2
Dependent Claim
124 words
In the fabrication of integrated circuits on a substrate wherein radiation is passed through a masking member to expose certain regions of a photosensitive layer, a process for forming an improved marker for permitting better alignment between said masking member and said substrate, comprising the steps of: forming a photoresist layer on said substrate; forming an opening in said layer at the proposed site of said marker; etching a depression in said substrate in said substrate at said opening, said depression including sloped sides and a generally planer bottom region; roughening said bottom region such that said bottom region directly reflects less radiation than said substrate surface; whereby a high contrast marker for use in aligning said masking member with said substrate is formed.
Claim 3
Dependent Claim
16 words
The process defined in claim 1 wherein a isotropic etchant is used in said etching step.
Claim 4
Dependent Claim
40 words
The process defined by claim 2 including the steps of removing said photoresist layer from said substrate and forming a second photoresist layer which covers said depression, said second layer having a uniform thickness over said surface of said substrate.
Claim 5
Dependent Claim
30 words
The process defined by claim 1 wherein the step of pitting said bottom region comprises subjecting said substrate to a plasma etching step for etching with an exposed anode electrode.
Claim 6
Dependent Claim
151 words
In the fabrication of integrated circuits on a substrate wherein radiation is passed through a masking member to expose certain regions of a photosensitive layer, a process for forming an improved contrast marker for permitting better alignment between said masking member and said substrate, comprising the steps of: forming a photoresist layer on said substrate; forming an opening on said layer at the proposed site of said marker; etching a depression in said substrate at said opening, said depression including sloped sides and a generally planer bottom region; roughening said bottom region such that said bottom region directly reflects less radiation than said substrate surface; removing said photoresist layer from said substrate; forming a second photoresist layer which covers said depression, said second layer having a uniform thickness over said surface of said substrate; whereby a high contrast marker for use in aligning said masking member with said substrate is formed.
Claim 7
Dependent Claim
151 words
In the fabrication of integrated circuits on a substrate wherein radiation is passed through a masking member to expose certain regions of a photosensitive layer, a process for forming an improved contrast marker for permitting better alignment between said masking member and said substrate, comprising the steps of: forming a photoresist layer on said substrate; forming an opening on said layer at the proposed site of said marker; etching a depression in said substrate at said opening, said depression including sloped sides and a generally planer bottom region; roughening said bottom region such that said bottom region directly reflects less radiation than said substrate surface; removing said photoresist layer from said substrate; forming a second photoresist layer which covers said depression, said second layer having a uniform thickness over said surface of said substrate; whereby a high contrast marker for use in aligning said masking member with said substrate is formed.
References Cited (Backward Citations)
US3171762A
Cited
US3802940A
Cited
US3787275A
Cited
US3783044A
Cited
US4106976A
Cited
US4233091A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-02-21 | 1986-08-23 | 1987-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-02-21 | 1990-08-23 | 1991-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-02-21 | 1994-08-23 | 1995-02-22 | $7700.00 | Window Closed / Lapsed |