US4374428A — Expandable FIFO system

Claim 1

Independent Claim 332 words

A FIFO system comprising an exandable number N of FIFO chips arranged to form a ring of identical FIFO chips connected in an identical manner and with each FIFO chip comprising: a RAM memory having N word storage locations; inboard pointing means which, when activated, points to, and directs the writing of words into, successive ones of said word storage locations with each word remaining in its word storage location until read out of the FIFO system; outboard pointing means which, when activated, points to, and directs the reading of words from, successive ones of said word storage locations; first control means responsive to the presence or absence of a word in the last word location in the RAM memory in any given FIFO chip to produce a first signal XO n =1 or a second signal XO n =0, respectively; second control means responsive to the presence or absence of a word in the last word location in the RAM memory in the FIFO chip immediately preceding said given FIFO chip in the ring of FIFO chips to produce a third signal XO n-1 =1 and a fourth signal XO n-1 =0, respectively; border transfer logic means resident in said each FIFO chip and connecting said each FIFO chip with the immediately preceding FIFO chip in said ring of FIFO chips and responsive to the presence of a word in the last word location in said preceding FIFO chip RAM memory (XO n-1 =1) to activate said inboard printing means in said given FIFO chip only when XO n =0 and to deactivate said inboard pointing means in said given FIFO chip when XO n =1 and further responsive to the absence of a word in the last word location in said preceding FIFO chip RAM memory (XO n-1 =0) to activate said outboard pointing means in said given FIFO chip when XO n =1, and to deactivate said outboard pointing means in said given FIFO chip when XO n =0.

Claim 2

Dependent Claim 332 words

A FIFO system comprising an exandable number N of FIFO chips arranged to form a ring of identical FIFO chips connected in an identical manner and with each FIFO chip comprising: a RAM memory having N word storage locations; inboard pointing means which, when activated, points to, and directs the writing of words into, successive ones of said word storage locations with each word remaining in its word storage location until read out of the FIFO system; outboard pointing means which, when activated, points to, and directs the reading of words from, successive ones of said word storage locations; first control means responsive to the presence or absence of a word in the last word location in the RAM memory in any given FIFO chip to produce a first signal XO n =1 or a second signal XO n =0, respectively; second control means responsive to the presence or absence of a word in the last word location in the RAM memory in the FIFO chip immediately preceding said given FIFO chip in the ring of FIFO chips to produce a third signal XO n-1 =1 and a fourth signal XO n-1 =0, respectively; border transfer logic means resident in said each FIFO chip and connecting said each FIFO chip with the immediately preceding FIFO chip in said ring of FIFO chips and responsive to the presence of a word in the last word location in said preceding FIFO chip RAM memory (XO n-1 =1) to activate said inboard printing means in said given FIFO chip only when XO n =0 and to deactivate said inboard pointing means in said given FIFO chip when XO n =1 and further responsive to the absence of a word in the last word location in said preceding FIFO chip RAM memory (XO n-1 =0) to activate said outboard pointing means in said given FIFO chip when XO n =1, and to deactivate said outboard pointing means in said given FIFO chip when XO n =0.

Claim 3

Dependent Claim 211 words

A FIFO system as in claim 1 in which said inboard pointing means and said outboard pointing means of each FIFO chip comprise: first and second counting means responsive, respectively, to the writing in or reading out of a word from the RAM memory of said each FIFO chip, to be incremented by a count of one, with each counting means having X+1 bit position stages with a count capacity of 2 X+1 , where 2 X =N; and in which said FIFO system further comprises: first comparing means responsive to the coincidence of the contents of the two least significant bit positions of said first and second counting means to produce a first comparing signal; second comparing means responsive to the coincidence or non-coincidence between the most significant bit position of said first and second counting means to produce second and third comparing signals, respectively; and gating means responsive to the coincident occurrence of said first comparing signal and said second comparing signal to produce a fourth output signal indicating the FIFO system is completely empty of words; said gating means further responsive to the coincident occurrence of said first signal and said third signal to produce a fifty output signal indicating the FIFO system is completely filled with words.

Claim 4

Dependent Claim 142 words

A FIFO system as in claim 1 in which each FIFO chip further comprises: first logic means including said first control means responsive to an activated inboard pointing means of said preceding FIFO chip overtaking an activated outboard pointing means of said given FIFO chip to indicate that all the word storage locations of said FIFO system have been filled and that no more words can be written therein until at least one word has been read therefrom; and said first logic means being further responsive to an activated outboard pointing means of said preceding FIFO chip overtaking an activated inboard pointing means of said given FIFO chip to indicate that all the word storage locations of said FIFO system have been emptied and that no more words can be read therefrom until at least one more word has been written therein.

Claim 5

Dependent Claim 185 words

A FIFO system as in claim 3 in which said inboard pointing means and said outboard pointing means of each FIFO chip comprise: first and second counting means, respectively, with each counting means having X+1 bit position stages with a count capacity of 2 X+1 , where 2 X =N; and in which said first logic means comprises: first comparing means responsive to the coincidence of the contents of the two least significant bit positions of said first and second counting means to produce a first comparing signal; second comparing means responsive to the coincidence or non-coincidence between the most significant bit position of said first and second counting means to produce second and third comparing signals, respectively; gating means responsive to the coincident occurrence of said first comparing signal and said second comparing signal to produce a fourth output signal indicating the FIFO system is completely empty of words; and said gating means further responsive to the coincident occurrence of said first comparing signal and said third comparing signal to produce a fifth output signal indicating the FIFO system is completely filled with words.

Claim 6

Dependent Claim 164 words

A FIFO system as in claim 1 in which said inboard pointing means of each FIFO chip comprises: counting means having at least X bit position stages, where 2 X =N, and being incremented by a count of X one each time a word is written into any given word location of the RAM memory of said each FIFO chip to then contain a count corresponding to the next word location following said given word location; a first plurality of gating means which, when energized in a given order, enable the writing of words into successive ones of said word locations; storage means for storing the count contained in said counting means for a time period δ which terminates prior to another word being written into said RAM memory; and second logic means comprising decoding means responsive to each successive count stored in said storage means during each of said time periods δ to energize each of said gating means in said given order.

Claim 7

Dependent Claim 165 words

A FIFO system as in claim 1 in which said outboard pointing means of each FIFO chip comprises: counting means having at least X bit position stages, where 2 X =N, and being incremented by a count of one each time a word is read out of any given word location of the RAM memory of said FIFO chip to then contain a count corresponding to the next word location following said given word location; a first plurality of gating means which, when energized in a given order, enable the reading of words out of successive ones of said word locations; storage means for storing the count contained in said counting means for a time period δ which terminates prior to another word being read out of said RAM memory; and second logic means comprising decoding means responsive to each successive count stored in said storage means during each of said time periods δ to energize each of said gating means in said given order.

Claim 8

Dependent Claim 212 words

In a data processing system requiring memory means for storing and retrieving data in a first in, first out (FIFO) order and having means for generating write in and read out instruction signals for writing words into or reading words from said memory means, a FIFO system comprising an expandable number of identical FIFO chips connected in identical manner to form a ring of FIFO chips with each chip comprising: a write in, read out memory having a plurality of word storage locations; inboard pointing means and outboard pointing means which, when activated, direct the writing in or reading out, respectively, or words into successive ones of said word storage locations with each written word remaining in the word storage location written into until read out from the system; and logic means including border transfer logic means connecting said each FIFO chip with the immediately preceding FIFO chip in said ring of FIFO chips and responsive to the presence or absence of words in both of the last word locations of said each FIFO chip memory and said preceding FIFO chip memory to inactivate said inboard or outboard pointing means, respectively, of said each FIFO chip and to deactivate the said inboard or outboard pointing means, respectively, of said preceding FIFO chip.

Claim 9

Dependent Claim 212 words

In a data processing system requiring memory means for storing and retrieving data in a first in, first out (FIFO) order and having means for generating write in and read out instruction signals for writing words into or reading words from said memory means, a FIFO system comprising an expandable number of identical FIFO chips connected in identical manner to form a ring of FIFO chips with each chip comprising: a write in, read out memory having a plurality of word storage locations; inboard pointing means and outboard pointing means which, when activated, direct the writing in or reading out, respectively, or words into successive ones of said word storage locations with each written word remaining in the word storage location written into until read out from the system; and logic means including border transfer logic means connecting said each FIFO chip with the immediately preceding FIFO chip in said ring of FIFO chips and responsive to the presence or absence of words in both of the last word locations of said each FIFO chip memory and said preceding FIFO chip memory to inactivate said inboard or outboard pointing means, respectively, of said each FIFO chip and to deactivate the said inboard or outboard pointing means, respectively, of said preceding FIFO chip.

Claim 10

Dependent Claim 88 words

A FIFO system as in claim 7 in which: said logic means is further responsive to the active inboard pointing means of said each FIFO chip over-taking activated outboard pointing means of said each FIFO chip to indicate that all the word storage locations of said FIFO system have been filled; and in which said logic means is still further responsive to said active outboard pointing means overtaking the activated inboard pointing means to indicate that all the word storage locations of said FIFO system have been emptied.

Claim 11

Dependent Claim 172 words

A FIFO system as in claim 8 in which said inboard pointing means and said outboard pointing means of each FIFO chip comprise: first and second counting means, respectively, with each counting means having X+1 position stages with a count capacity of 2 X+1 , where 2 X =N; and in which said logic means further comprises: first comparing means responsive to the coincidenct between the contents of the two least significant bit positions of said first and second counting means to produce a first signal; second comparing means responsive to the coincidence and non-coincidence between the most significant bit positions of said first and second counting means to produce second and third signals, respectively; gating means responsive to the coincident occurrence of said first and second signals to produce a fourth signal indicating the FIFO system is completely empty of words; and said gating means further responsive to the coincident occurrence of said first and third signals to produce a fifth signal indicating the FIFO system is completely filled with words.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1986-02-14	1986-08-16	1987-02-15	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1990-02-14	1990-08-16	1991-02-15	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1994-02-14	1994-08-16	1995-02-15	$7700.00	Window Closed / Lapsed

Expandable FIFO system

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