Circulating page loose system

Claim 2

A programmable network for simultaneously processing sets of variables, comprising: a plurality of registers X for holding page variables x i ; a plurality of registers X' for holding auxiliary variables x' i ; a plurality of registers U for holding input data u i ; a plurality of registers W for holding program words w j ,i ; decoding means having an input receiving said program words w j ,i and providing a plurality of outputs having control signals thereon; control lines connected with said plurality of outputs of said decoding means for carrying control signals therefrom; a plurality of operational means capable of performing arithmetic and logical functions, each said operational means having function-control inputs connected to said control lines, an output connected to the input of one of said registers X and X' to supply resulting data thereto, and inputs multiplexed to the outputs of said registers X, X', and U with said multiplexing being controlled by said control signals carried by said control lines; and timing means, responsive to said control signals carried by said control lines, for establishing a cycle of operation by clocking said resulting data into said registers X and X', with the termination of each said cycle causing a new program word w j ,i to be fed to said input of said decoding means whereby, for each said cycle, new values are simultaneously produced and stored in said registers X and X' as a function of the previous values in said registers X and X', of the values in said registers U, and of the content of program words w j ,i fed to said input of said decoding means.

Claim 3

The programable network of claim 1 wherein each of said plurality of registers X, X', and U includes capacity to store at least four binary digits with each said register X having an operational means multiplexed to at least one register X', one register U, and another register X, and with at least one said register X having said operational means further multiplexed to all other said registers X.

Claim 4

The programmable network of claim 1 wherein said decoding means includes: a plurality of first and second bistable elements with each of said first bistable elements being connected in cascade with a different one of said second bistable elements, and with each of said first bistable elements having an input connected to one output of said decoding means and each of said second bistable elements having an output connected to one of said control lines; means for simultaneously resetting all of said first bistable elements at the beginning of a sequence of said program words w j ,i received by said input of said decoding means; means for individually setting said first bistable elements when an activating control signal arrives at said input of said first bistable elements from said decoding means; and means for parallel transfering the content of all said first bistable elements into said second bistable element connected therewith at the end of said sequence of program words w j ,i fed to said input of said decoding means so that said programmable network, responsive to said control signals carried by said control lines, executes, in a single cycle, all the operations prescribed by each word w j ,i of said sequence, while a next sequence of words w j ,i is being utilized to introduce new content into said first bistable elements.

Claim 5

The programmable network of claim 3 wherein said decoding means includes: an electrically-alterable-read-only-memory (EAROM) with data inputs and outputs and having address inputs receiving said program words w j ,i ; a plurality of totempole digital switches each of which has a first input connected jointly with one said data input of said EAROM and to the output of one of said second bistable elements, a second input connected to the data output of said EAROM that corresponds to said data input of said EAROM, and an output connected to one of said control lines; means for writing into said EAROM the content of said second bistable elements accumulated from a sequence of program words w j ,i fed to said input of said decoding means after recognition of specific program words w j ,i a part of which is fed to said address input of said EAROM; and means for recognizing other specific program words w j ,i, and consequently feeding part of these words to said address input of said EAROM and positioning said totempole switches to their second input so that program words are read from said EAROM to produce control signals in said control lines responsive to single program words w j ,i fed to said input of said decoding means.

Claim 6

A data processing apparatus, comprising: a programmable network having: a plurality of registers X for holding page variables x i ; a plurality of registers X' for holding auxiliary variables x' i ; a plurality of registers U for holding input data u i ; a plurality of registers W FT for holding programs words w F ,i and w T ,i ; first decoding means having an input receiving said program words w F ,i and w T ,i and providing a plurality of outputs having control signals thereof; control lines connected with said plurality of outputs of said first decoding means for carrying control signals therefrom; a plurality of operational means capable of performing arithmetic and logical functions, each said operational means having function-control inputs connected to said control lines, an output connected to the input of one of said registers X and X' to supply data thereto, and inputs multiplexed to the outputs of said registers X, X', and U with said multiplexing being controlled by said control signals carried by said control lines; first timing means, responsive to said control signals carried by said control lines, for establishing a cycle of operation by clocking said data into said registers X and X', with the termination of each said cycle causing a new program word w F ,i and w T ,i to be fed to said input of said first decoding means whereby, for each said cycle, new values are simultaneously produced and stored in said registers X and X' as a function of the previous values in said registers X and X', of the values in said registers U, and of the content of program words w T ,i fed to said input of said first decoding means; a register K for holding a key word including a state label; means for updating said state label as a function of the then present values in said registers X, X', and U, and of the content of program words w T ,i fed to said input of said first decoding means; and a plurality of registers W R for holding program words w R ,i ; a packer having: pluralities of registers x P , W R P , and a register K P , all of said registers having one-to-one correspondence with respect to said registers X, W R , and K of said programmable network; means for operatively transfering in parallel the content of said registers X, K, and W R of said programmable network into said corresponding registers X P , K P , and W R P of said packer; an output buffer with an input; a packer bus connected to the ouput of said registers X P and K P and to said input of said output buffer; second timing means for establishing a packer cycle in which the content of said registers X P and K P are transfered one at a time into said packer bus, in conjunction with production of a page-auxiliary-signal, at the beginning of said packer cycle, and a word-auxiliary signal at the transfer of the content from each said register X P ; and second decoding means receiving program words w R ,i from said W R P registers for skipping the transfer of a specific variable x i from said register X P to said packer bus responsive to specific program words w R ,i, altering the order sequence of said transfering of variables x i to said packer bus responsive to other specific program words w R ,i, and transfering specific variables x i in said registers X P into said output buffer responsive to further specific program words w R ,i ; a page memory, having: a serial storage with a data input connected to said packer bus and an auxiliary signal input receiving said page- and word- auxiliary-signals, and a data and auxiliary-signal outputs; and means for feeding into said serial storage a page of data, comprising said key word, said page variables x i and said auxiliary signals, for each cycle of the packer; a program memory with an output, addressable in blocks of program words w I ,i, w F ,i, w T ,i, and w R ,i ; and an assembler having: pluralities of registers X A , U A , W FT A , W R A , and a register K A , all of said registers having a one-to-one correspondence with respect to said registers X, U, w FT , W R , and K, respectively, of said programmable network; a plurality of registers W I A ; an assembler bus connected to said data output of said page memory and to the input of said registers K A and X A ; a program bus connected to said output of said program memory and to the input of said registers W FT A , W I A , and W R A ; an input data bus connected to the input of said registers U A ; third timing means for establishing an assembler cycle, responsive to the page- and word- auxiliary-signals from said auxiliary-signal output of said page memory, for transferring into said registers K A and X A from said assembler bus a page of data including a key word and a plurality of page variables x i ; control means for fetching a block of program words w I ,i, w F ,i, w T ,i, and w R ,i into said registers, W I , W FT A , and W R A respectively, from said program memory, addressed by said state label in said register K A , control means for fetching input data u i into said registers U A , responsive to content in said registers W I ; and means for transferring in parallel the page of data held by registers K A , X A , U A , W FT A , and W R A into the corresponding registers K, X, U, W FT , and W R of the programmable network; whereby a plurality of said pages, acquiring program blocks, responsive to the present state label, and new data in said assembler, executing operations, exchanging data through the registers X', and updating the state label in said programmable network, and routing data into said output buffer in said packer, carry out a plurality of independent and dependent processes.

Claim 7

A data processing apparatus, comprising: a programmable network having: a plurality of registers X for holding page variables x i ; a plurality of registers X' for holding auxiliary variables x' i ; a plurality of registers U for holding input data u i ; a plurality of registers W FT for holding programs words w F ,i and w T ,i ; first decoding means having an input receiving said program words w F ,i and w T ,i and providing a plurality of outputs having control signals thereof; control lines connected with said plurality of outputs of said first decoding means for carrying control signals therefrom; a plurality of operational means capable of performing arithmetic and logical functions, each said operational means having function-control inputs connected to said control lines, an output connected to the input of one of said registers X and X' to supply data thereto, and inputs multiplexed to the outputs of said registers X, X', and U with said multiplexing being controlled by said control signals carried by said control lines; first timing means, responsive to said control signals carried by said control lines, for establishing a cycle of operation by clocking said data into said registers X and X', with the termination of each said cycle causing a new program word w F ,i and w T ,i to be fed to said input of said first decoding means whereby, for each said cycle, new values are simultaneously produced and stored in said registers X and X' as a function of the previous values in said registers X and X', of the values in said registers U, and of the content of program words w T ,i fed to said input of said first decoding means; a register K for holding a key word including a state label; means for updating said state label as a function of the then present values in said registers X, X', and U, and of the content of program words w T ,i fed to said input of said first decoding means; and a plurality of registers W R for holding program words w R ,i ; a packer having: pluralities of registers x P , W R P , and a register K P , all of said registers having one-to-one correspondence with respect to said registers X, W R , and K of said programmable network; means for operatively transfering in parallel the content of said registers X, K, and W R of said programmable network into said corresponding registers X P , K P , and W R P of said packer; an output buffer with an input; a packer bus connected to the ouput of said registers X P and K P and to said input of said output buffer; second timing means for establishing a packer cycle in which the content of said registers X P and K P are transfered one at a time into said packer bus, in conjunction with production of a page-auxiliary-signal, at the beginning of said packer cycle, and a word-auxiliary signal at the transfer of the content from each said register X P ; and second decoding means receiving program words w R ,i from said W R P registers for skipping the transfer of a specific variable x i from said register X P to said packer bus responsive to specific program words w R ,i, altering the order sequence of said transfering of variables x i to said packer bus responsive to other specific program words w R ,i, and transfering specific variables x i in said registers X P into said output buffer responsive to further specific program words w R ,i ; a page memory, having: a serial storage with a data input connected to said packer bus and an auxiliary signal input receiving said page- and word- auxiliary-signals, and a data and auxiliary-signal outputs; and means for feeding into said serial storage a page of data, comprising said key word, said page variables x i and said auxiliary signals, for each cycle of the packer; a program memory with an output, addressable in blocks of program words w I ,i, w F ,i, w T ,i, and w R ,i ; and an assembler having: pluralities of registers X A , U A , W FT A , W R A , and a register K A , all of said registers having a one-to-one correspondence with respect to said registers X, U, w FT , W R , and K, respectively, of said programmable network; a plurality of registers W I A ; an assembler bus connected to said data output of said page memory and to the input of said registers K A and X A ; a program bus connected to said output of said program memory and to the input of said registers W FT A , W I A , and W R A ; an input data bus connected to the input of said registers U A ; third timing means for establishing an assembler cycle, responsive to the page- and word- auxiliary-signals from said auxiliary-signal output of said page memory, for transferring into said registers K A and X A from said assembler bus a page of data including a key word and a plurality of page variables x i ; control means for fetching a block of program words w I ,i, w F ,i, w T ,i, and w R ,i into said registers, W I , W FT A , and W R A respectively, from said program memory, addressed by said state label in said register K A , control means for fetching input data u i into said registers U A , responsive to content in said registers W I ; and means for transferring in parallel the page of data held by registers K A , X A , U A , W FT A , and W R A into the corresponding registers K, X, U, W FT , and W R of the programmable network; whereby a plurality of said pages, acquiring program blocks, responsive to the present state label, and new data in said assembler, executing operations, exchanging data through the registers X', and updating the state label in said programmable network, and routing data into said output buffer in said packer, carry out a plurality of independent and dependent processes.

Claim 8

The data processing apparatus of claim 5 wherein said apparatus includes a FIFO page memory implemented with a random access storage, comprising: a write-counter, and a read-counter; means for multiplexing the address of said random access storage to said write-counter while writing words from said packer, and to said read-counter while reading by part of said assembler; and means for incrementing by one said write-counter for each word written, and incrementing by one said read-counter for each word read, being said counting circular; so to relocate in adjacent storage locations, circulating pages of changing size.

Claim 9

The data processing apparatus of claim 6 wherein said FIFO page memory further includes: a first adder with an output connected to the address lines of said random access storage, and a first input connected to said write-counter while writing and to said read-counter while reading; a second adder with an output connected to a second input of said first adder, a first input connected to a reservation-register, and a second input connected to the output of an accumulator; a boundary-register with output connected to the input of said accumulator and to the input of a comparator whose other input is connected to said address lines of said randon access storage; first, second, and third sets of registers, for interchanging content with said write-counter, read-counter and boundary-register, respectively; means for transferring words from said packer into said reservation, boundary and first, second and third sets of registers responsive to specific codes in said registers W R P of said packer; and means for interchanging the content between the write-counter, read-counter, and boundary-register and their corresponding registers, responsive to specific said control signals of the packer, whereby at each transfer the previous content in said boundary-register is added to the content in said accumulator, and wherein, at each equality recognized by said comparator, said write-counter or read-counter is reset, whichever executed the last increment by one so that said random access storage is caused to be partitioned in a reserved region, determined by the content in said reservation-register, and in several segments of circulating pages, determined by the content in said boundary-register and its interchanging registers.

Claim 10

The data processing apparatus of claim 5 wherein said packer bus transmits data pages, wherein said packer includes means for producing control signals responsive to content in said registers W R P , and wherein said apparatus includes: a page FIFO storage with input connected to said packer bus; a randon access storage; a controllable functional element with first and second inputs, and an output connected to the input of said random access storage; an address register with an input connected to said packer bus and an output addressing said random access storage; a data register with an input connected to said packer bus and an output connected to said first input of said functional element; a buffer register with an input connected to the output of said random access storage and an output connected to said second input of said functional element; first transfer means for transferring a first word into said address register and another word into said data register from said packer bus; second transfer means for transferring into said buffer register the content addressed in said random access storage; third transfer means for transferring into the addressed location of said random access storage the content at the output of said functional element; fourth transfer means for transferring the content addressed in said random access storage into the present input location of said page FIFO storage, said first, second, third and fourth transfers being responsive to specific ones of said control signals of said packer; whereby data from said pages is selectively stored in said random access storage according to predetermined functions, and whereby data is transferred from said random access storage into said pages.

Claim 11

The data processing apparatus of claim 5 wherein said packer has serial binary-data output and means for producing an auxiliary signal, wherein said assembler has serial binary-data input and means for receiving an auxiliary signal, and wherein said apparatus also includes: a transmission channel carrying three orthogonal waveforms; and input and output means in said channel for generating and selectively detecting said three waveforms, connected to said packer outputs and assemble inputs, respectively, so that two said waveforms are related to the two values of the binary data, and one said waveform is related to the presence of said auxiliary signal.

Claim 14

The method of claim 10 wherein one said code F in said program blocks includes a state label and instruction of depositing it in said programable network so that a successive page having said state label substituted therein disregards its own codes T and acquires said state label deposited in the programable network; one said code T in said program block includes an indication of priority; and one said state label comprises a sequence of pairs of items, whereby the first item in each pair is a state label and the second item a number, so that a page with such a state label, in its successive said steps acquires a program block in accordance with said first item in the first said pair, for as many steps as the number constituting said second item in the pair, and disregards responding to said codes T of the acquired program block except for such codes T which carry said priority indication and except if a said deposited state label is present in the programable network, and repeating said described program acquisition for all successive pairs in said sequence of pairs.

Claim 15

The method of claim 10 wherein one said code R in said program block includes the indication of a state label, thereby said code R is executed only if the newly selected state label in the page equals said state label indicated in said code R.