← Back to Patent Explorer
US4374392A Expired / Lapsed US ⏱️ 0.0 years remaining

Monolithic integrated circuit interconnection and fabrication method

Assignee: Lockheed Martin Corp
•
Filing: 1980-11-25
•
Granted: 1983-02-15
•
Expires: 2000-11-25
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A monolithic integrated circuit incorporates a substrate of III-V material having an interconnection pattern disposed on a surface thereof. An epitaxial layer is grown on the substrate surface such that it overgrows the interconnection pattern, and a plurality of circuit elements, formed on the surface of the epitaxial layer, are interconnected by contacts which extend from the epitaxial layer surface to the underlying interconnection pattern.

Inventors

  • 👤 Walter F. Reichert

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 17:51
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/20; H10W20/01; H10W20/021

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 54 words
A monolithic integrated circuit, comprising: a substrate of III-V material having a surface; an interconnection pattern disposed on the substrate surface; an epitaxial layer disposed on the substrate surface and the interconnection pattern; and a plurality of circuit elements disposed on the epitaxial surface, each element having a portion which contacts the interconnection pattern.
Claim 2
Dependent Claim 54 words
A monolithic integrated circuit, comprising: a substrate of III-V material having a surface; an interconnection pattern disposed on the substrate surface; an epitaxial layer disposed on the substrate surface and the interconnection pattern; and a plurality of circuit elements disposed on the epitaxial surface, each element having a portion which contacts the interconnection pattern.
Claim 3
Dependent Claim 12 words
A circuit in accordance with claim 1, wherein: the substrate is GaAs.
Claim 4
Dependent Claim 20 words
A circuit in accordance with claim 1, wherein: the interconnection pattern comprises a relatively thin film of a refractory material.
Claim 5
Dependent Claim 21 words
A circuit in accordance with claim 3, wherein: the refractory metal is selected from the group consisting of molybdenum and tungsten.
Claim 6
Dependent Claim 22 words
A circuit in accordance with claim 1, wherein: the circuit elements contact the interconnection pattern via metallized openings in the epitaxial layer.
Claim 7
Dependent Claim 29 words
A circuit in accordance with claim 1, wherein: the epitaxial layer includes a buffer layer disposed on the substrate surface and an active layer disposed on the buffer layer.
Claim 8
Dependent Claim 41 words
A circuit in accordance with claims 1 or 6, further comprising: an FET having spaced source, gate and drain electrodes on the epitaxial layer; the source electrode contacting a first interconnection pattern; and the drain electrode contacting a second interconnection pattern.

References Cited (Backward Citations)

US3593068A Cited
US3641661A Cited
US4141021A Cited
US4226649A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1986-02-14 1986-08-16 1987-02-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1990-02-14 1990-08-16 1991-02-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1994-02-14 1994-08-16 1995-02-15 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag