US4373141A
Expired / Lapsed
US
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Fast updating peak detector circuit
Assignee: Raytheon Co
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Filing: 1981-01-22
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Granted: 1983-02-08
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Expires: 2001-01-22
Abstract
Abstract A peak detector circuit (10) is disclosed wherein an input signal is full-wave rectified by a circuit (14) and the rectified signal is provided simultaneously to peak detect, hold and dump circuits (18), (20). Each of the peak detect, hold and dump circuits is discharged at the start of periodic intervals with a phase offset between the intervals for the two circuits. The peak signals are discharged at essentially the start of the interval followed by rapid charging of the peak signal to the peak amplitude of the rectified input signal. The later portions of each of the intervals of the peak signals produced by the peak detect, hold and dump circuits (18) and (20) are transmitted alternately through a multiplexer circuit (24). The resulting output signal is transmitted through a high impedance buffer amplifier (30) to an output terminal (32) of peak detector circuit (10). The timing of the operation of multiplexer (24) serves to remove the discharge and charge transitions of the peak signals from the peak detected output signal.
Inventors
- 👤 David E. Sanders
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:07
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/02; G11C27/024; G11C27/026
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
121 words
A peak detector circuit, comprising: means for rectifying an input signal to produce a rectified signal; first means connected to receive said rectified signal for detecting and holding the peak amplitude of said rectified signal to produce a first peak signal; second means connected to receive said rectified signal concurrently with said first means for detecting and holding the peak amplitude of said rectified signal to produce a second peak signal; means for alternately connecting said first and second peak signals to an output terminal; and means for alternately resetting said first and second peak signals to a preset level wherein each of said peak signals is reset when the other of said peak signals is connected to said output terminal.
Claim 2
Dependent Claim
121 words
A peak detector circuit, comprising: means for rectifying an input signal to produce a rectified signal; first means connected to receive said rectified signal for detecting and holding the peak amplitude of said rectified signal to produce a first peak signal; second means connected to receive said rectified signal concurrently with said first means for detecting and holding the peak amplitude of said rectified signal to produce a second peak signal; means for alternately connecting said first and second peak signals to an output terminal; and means for alternately resetting said first and second peak signals to a preset level wherein each of said peak signals is reset when the other of said peak signals is connected to said output terminal.
Claim 3
Dependent Claim
18 words
The peak detector circuit recited in claim 1 wherein said means for rectifying comprises a full wave rectifier.
Claim 4
Dependent Claim
38 words
The peak detector circuit recited in claim 1 wherein said first and said second means for detecting each comprises the combination of a diode connected to receive said rectified signal for charging a capacitor connected to said diode.
Claim 5
Dependent Claim
40 words
The peak detector circuit recited in claim 3 wherein said means for resetting comprises a switch for shorting each of said capacitors, each switch operated by a separate pulse signal, each said pulse signal out-of-phase with the other pulse signal.
Claim 6
Dependent Claim
85 words
The peak detector circuit recited in claim 1 wherein said means for alternately connecting comprises first and second switches having the inputs thereof connected to receive said first and second peak signals respectively, said switches having the outputs thereof connected to said output terminal, said switches connected respectively to receive first and second clock signals, said first and second switches driven by said first and second clock signals respectively, said first clock signal at approximately the same rate but out-of-phase with said second clock signal.
Claim 7
Dependent Claim
142 words
A peak detector circuit, comprising: a full-wave rectifier connected to receive an input signal and produce a full-wave rectified signal; a first peak detect and hold circuit connected to receive said rectified signal and hold the peak amplitude thereof as a first peak signal; a second peak detect and hold circuit connected to receive said rectified signal concurrently with said first peak detect and hold circuit and hold the peak amplitude thereof as a second peak signal; switch means operated in response to a reference clock signal for alternately connecting said first and said second peak signals to an output terminal; and means responsive to said reference clock signal for alternately and periodically pulling said first and said second peak signals to a common potential wherein the peak signal being pulled to the common potential is not connected to said output terminal.
Claim 8
Dependent Claim
142 words
A peak detector circuit, comprising: a full-wave rectifier connected to receive an input signal and produce a full-wave rectified signal; a first peak detect and hold circuit connected to receive said rectified signal and hold the peak amplitude thereof as a first peak signal; a second peak detect and hold circuit connected to receive said rectified signal concurrently with said first peak detect and hold circuit and hold the peak amplitude thereof as a second peak signal; switch means operated in response to a reference clock signal for alternately connecting said first and said second peak signals to an output terminal; and means responsive to said reference clock signal for alternately and periodically pulling said first and said second peak signals to a common potential wherein the peak signal being pulled to the common potential is not connected to said output terminal.
Claim 9
Dependent Claim
55 words
The peak detector circuit recited in claim 6 wherein said means for pulling said first and said second peak signals to a common potential comprises first and second switches operated by phase offset clock signals derived from said reference clock signal, said means for pulling for alternately discharging said first and said second peak signals.
Claim 10
Independent Claim
103 words
A method for peak detecting an input signal, comprising the steps of: rectifying said input signal to produce a rectified input signal; detecting and holding the peak amplitude of said rectified input signal to produce a first peak signal; detecting and holding the peak amplitude of said rectified input signal to produce a second peak signal concurrent with producing said first peak signal; alternately connecting said first and said second peak amplitude signals to an output terminal, and periodically resetting each of said peak signals to a preset level at a time when the peak signal is not connected to said output terminal.
Claim 11
Independent Claim
103 words
A method for peak detecting an input signal, comprising the steps of: rectifying said input signal to produce a rectified input signal; detecting and holding the peak amplitude of said rectified input signal to produce a first peak signal; detecting and holding the peak amplitude of said rectified input signal to produce a second peak signal concurrent with producing said first peak signal; alternately connecting said first and said second peak amplitude signals to an output terminal, and periodically resetting each of said peak signals to a preset level at a time when the peak signal is not connected to said output terminal.
Claim 12
Dependent Claim
27 words
The method recited in claim 8 wherein said steps of detecting and holding each comprises applying said rectified input signal through a diode to charge a capacitor.
Claim 13
Dependent Claim
18 words
The method recited in claim 9 wherein the step of resetting comprises periodically and alternately discharging said capacitors.
Claim 14
Independent Claim
110 words
A method for peak detecting an input signal, comprising the steps of: full-wave rectifying the input signal to produce a rectified input signal; detecting and holding the peak amplitude of said rectified input signal to produce a first peak signal; detecting and holding the peak amplitude of said rectified input signal to produce a second peak signal, said second peak signal produced concurrently with said first peak signal; resetting each of said peak signals to ground potential in response to a clock signal, and alternately connecting each of said peak signals to an output terminal wherein said resetting occurs when the peak signal is not connected to said output terminal.
Claim 15
Independent Claim
110 words
A method for peak detecting an input signal, comprising the steps of: full-wave rectifying the input signal to produce a rectified input signal; detecting and holding the peak amplitude of said rectified input signal to produce a first peak signal; detecting and holding the peak amplitude of said rectified input signal to produce a second peak signal, said second peak signal produced concurrently with said first peak signal; resetting each of said peak signals to ground potential in response to a clock signal, and alternately connecting each of said peak signals to an output terminal wherein said resetting occurs when the peak signal is not connected to said output terminal.
Claim 16
Dependent Claim
27 words
The method recited in claim 11 wherein the steps of detecting and holding each comprises routing said rectified input signal through a diode to charge a capacitor.
Claim 17
Dependent Claim
70 words
The method recited in claim 11 wherein said first peak signal is produced during first periodic intervals and said second peak signal is produced during second periodic intervals, said first and second periodic intervals being offset by approximately 180°, said peak signals being connected to said output terminal during a second half of each of said intervals and said resetting occurring during a first half of each of said intervals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-02-07 | 1986-08-09 | 1987-02-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-02-07 | 1990-08-09 | 1991-02-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-02-07 | 1994-08-09 | 1995-02-08 | $7700.00 | Window Closed / Lapsed |