US3710141A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sample and hold circuit
Assignee: INTER COMPUTER ELECTRONICS Inc
•
Filing: 1971-07-23
•
Granted: 1973-01-09
•
Expires: 1991-07-23
Abstract
Abstract A circuit for sampling a waveform voltage during a predetermined small sample time period and then holding the sampled voltage for a long hold period relative to the sample period. A waveform signal is impressed at the input of a diode bridge. A storage or hold capacitor is connected at the output of the bridge. A zener diode having a zener or breakover voltage greater than the voltage of the waveform, prevents current flow through the bridge during the hold period. The leading edge of a trigger pulse forward biases the bridge and overcomes the zener voltage, to enable the storage capacitor to reach a voltage level equal to the instantaneous voltage appearing at the bridge input. The trailing edge of the pulse turns ''''off'''' the bridge, and the zener voltage of the zener diode holds the bridge ''''off'''' until the next trigger pulse.
Inventors
- 👤 K Zeiger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 08:33
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/02
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
311 words
In a circuit for sampling and holding a voltage of a waveform signal including an input means for receiving said signal, sampling means for sampling a portion of said signal, a storage capacitor means for storing a voltage corresponding to the voltage of said portion of the signal, and an output means for connecting said stored portion of the signal to an output point, said sampling means comprising: a bridge having a first, second, third and fourth substantially unidirectional conductive devices, each of said devices having an anode and a cathode, the cathode side of the first device being connected to the anode side of the second device at a first terminal and the cathode side of the third device being connected to anode side of the fourth device at a second terminal, the anode sides of the first and third devices being connected together at a first point and the cathode sides of the second and fourth devices being connected together at a second point, said input means being connected to said first terminal and said storage capacitor being connected to said second terminal; a zener diode interposed between said points of the bridge; a transistor means having an input and an output, said input receiving a drive pulse to turn ''''on'''' the transistor means for generating a trigger pulse; a transformer means having a primary side coupled to the output of said transistor means, and a secondary side coupled to said switch means, said transformer means coupling said trigger pulse from the output to said switch means to forward bias said bridge and cause conduction through said zener diode, and an unterminated delay line having a center conductor connected to the output of the transistor means, the primary of said transformer means being coupled to said center conductor, energy reflected along said delay line turning ''''off'''' said transistor means.
Claim 2
Dependent Claim
311 words
In a circuit for sampling and holding a voltage of a waveform signal including an input means for receiving said signal, sampling means for sampling a portion of said signal, a storage capacitor means for storing a voltage corresponding to the voltage of said portion of the signal, and an output means for connecting said stored portion of the signal to an output point, said sampling means comprising: a bridge having a first, second, third and fourth substantially unidirectional conductive devices, each of said devices having an anode and a cathode, the cathode side of the first device being connected to the anode side of the second device at a first terminal and the cathode side of the third device being connected to anode side of the fourth device at a second terminal, the anode sides of the first and third devices being connected together at a first point and the cathode sides of the second and fourth devices being connected together at a second point, said input means being connected to said first terminal and said storage capacitor being connected to said second terminal; a zener diode interposed between said points of the bridge; a transistor means having an input and an output, said input receiving a drive pulse to turn ''''on'''' the transistor means for generating a trigger pulse; a transformer means having a primary side coupled to the output of said transistor means, and a secondary side coupled to said switch means, said transformer means coupling said trigger pulse from the output to said switch means to forward bias said bridge and cause conduction through said zener diode, and an unterminated delay line having a center conductor connected to the output of the transistor means, the primary of said transformer means being coupled to said center conductor, energy reflected along said delay line turning ''''off'''' said transistor means.
Claim 3
Dependent Claim
61 words
The circuit of claim 1 includes a signal inverter means having an input and an output, the input of the inverter being coupled to the input of the bridge to receive voltage variations of said signal, the output of the inverter providing signals to cancel leakage signals coupling through the bridge via capacitance between the input and output of the bridge.
Claim 4
Dependent Claim
36 words
The circuit of claim 1, wherein said delay line includes an electrical conductive sheath encircling said center conductor, said primary of the transformer means being connected to said sheath to capacitively couple with said center conductor.
Claim 5
Dependent Claim
23 words
The circuit of claim 3, wherein said transistor means comprises a mesa transistor, said drive pulse driving the mesa transistor into avalanche mode.
Claim 6
Dependent Claim
28 words
The circuit of claim 4, wherein amplifier means is coupled to said transistor means for generating said drive pulse, said amplifier means including at least one non-saturating amplifier.
Claim 7
Dependent Claim
64 words
The circuit of claim 5, wherein said non-saturating amplifier means includes a second transistor having a collector, emitter and base terminals; means connected to the base terminal and one of the other of said second transistor terminals to prevent the second transistor from saturating; and means connected to said other terminal to prevent the voltage between said other terminal from exceeding a predetermined level.
Claim 8
Dependent Claim
73 words
The circuit of claim 6, wherein: a first diode member is coupled on one end to the collector; and a second diode and a tHird diode are connected in series, said third diode being connected to the base and said second diode being connected to the opposite end of the first diode, said diode members preventing the voltage between the collector and base of the second transistor from falling below a predetermined level.
Claim 9
Dependent Claim
28 words
The circuit of claim 7, wherein a zener diode is associated with the collector terminal to prevent the voltage at the collector terminal from exceeding said predetermined level.
Claim 10
Dependent Claim
39 words
the circuit of claim 7, wherein a substantially constant voltage source is coupled to the collector whereby current conducts between the collector and the voltage source to prevent the voltage between collector and base from exceeding said predetermined level.
Claim 11
Dependent Claim
32 words
The circuit of claim 6, wherein a field effect transistor (''''FET'''') source follower means is connected to the storage capacitor, said source follower providing a high input impedance to the storage capacitor.
Claim 12
Dependent Claim
43 words
The circuit of claim 10, wherein a common collector amplifier means is connected to said source follower to provide a high input impedance to the source follower and a low output impedance, said common collector amplifier including a balanced PNP and NPN circuit.
Claim 13
Dependent Claim
29 words
The circuit of claim 10, wherein a second field effect transistor is connected in the source circuit of the source follower to control current flow through the source follower.
Claim 14
Dependent Claim
28 words
The circuit of claim 6, wherein a balanced common collector amplifier is coupled to the input of the bridge to provide a low output impedance to the bridge.
Claim 15
Dependent Claim
193 words
In a circuit for sampling and holding a voltage of a waveform signal including an input means for receiving said signal, sampling means for sampling a portion of said signal, a storage capacitor means for storing a voltage corresponding to the voltage of said portion of the signal, and an output means for connecting said stored portion of the signal to an output point, said sampling means comprising: a switch means including an input end connected to the output of said input means and an output end connected to said storage capacitor means, said switch means having an on-condition and an off-condition, said switch means permitting current flow between the input means and the storage capacitor to enable said capacitor to charge substantially to the voltage level simultaneously appearing at said input end, and a trigger means for switching said switch means to the on-condition for a predetermined time duration and switching said switch means to the off-condition after said duration, including an unterminated delay line receiving an input signal when the switch means is switched to its on-condition and delivering a delayed reflected signal for switching said switch means to its off-condition.
Claim 16
Dependent Claim
193 words
In a circuit for sampling and holding a voltage of a waveform signal including an input means for receiving said signal, sampling means for sampling a portion of said signal, a storage capacitor means for storing a voltage corresponding to the voltage of said portion of the signal, and an output means for connecting said stored portion of the signal to an output point, said sampling means comprising: a switch means including an input end connected to the output of said input means and an output end connected to said storage capacitor means, said switch means having an on-condition and an off-condition, said switch means permitting current flow between the input means and the storage capacitor to enable said capacitor to charge substantially to the voltage level simultaneously appearing at said input end, and a trigger means for switching said switch means to the on-condition for a predetermined time duration and switching said switch means to the off-condition after said duration, including an unterminated delay line receiving an input signal when the switch means is switched to its on-condition and delivering a delayed reflected signal for switching said switch means to its off-condition.
Claim 17
Dependent Claim
61 words
The circuit of claim 14 includes a signal inverter means having an input and an output, the input of the inverter being coupled to the input of the bridge to receive voltage variations of said signal, the output of the inverter providing signals to cancel leakage signals coupling through the bridge via capacitance between the input and output of the bridge.
Claim 18
Dependent Claim
176 words
The sample and hold circuit of claim 14, wherein said switch means includes: a bridge having a first, second, third and fourth substantially unidirectional conductive devices, each of said devices having an anode and a cathode, the cathode side of the first device being connected to the anode side of the second device at a first terminal and the cathode side of the third device being connected to the anode side of the fourth device at a second terminal, the anode sides of the first and third devices being connected together at a first point and the cathode sides of the second and fourth devices being connected together at a second point, said input means being connected to said first terminal and said storage capacitor being connected to said second terminal; and a switch member interposed between said bridge and said trigger mEans, said switch member having an on-condition and an off-condition, said switch member enabling current flow through said bridge when in the on-condition, said trigger means causing said switch member to switch the on-condition.
Claim 19
Dependent Claim
43 words
The circuit of claim 16, wherein said switch member comprises a zener diode having one end connected to one of said points, the zener voltage of said zener diode being greater than the voltage of the analog signal appearing at said first terminal.
Claim 20
Dependent Claim
75 words
The circuit of claim 17, wherein said trigger means includes means for providing a trigger pulse having a voltage on the leading edge greater than the zener voltage, said trigger pulse forward biasing the bridge and overcoming said zener voltage to enable current conduction through the bridge and said zener diode, the trailing edge of said trigger pulse causing said bridge and zener diode to bias ''''off'''' and thereby preventing current flow through the bridge.
Claim 21
Dependent Claim
87 words
The circuit of claim 18, wherein said trigger means includes: a transistor means having an input and an output, said input receiving a drive pulse to turn ''''on'''' the transistor means for generating said trigger pulse; and a transformer means having a primary side coupled to the output of said transistor means, and a second side coupled to said switch means, said transformer means coupling said trigger pulse from the output to said switch means to forward bias said bridge and cause conduction through said zener diode.
Claim 22
Dependent Claim
50 words
The circuit of claim 19, wherein said trigger means further includes an unterminated delay line having a center conductor connected to the output of the transistor means, the primary of said transformer means being coupled to said center conductor, energy reflected along said delay line turning ''''off'''' said transistor means.
Claim 23
Dependent Claim
36 words
The circuit of claim 20, wherein said delay line includes an electrical conductive sheath encircling said center conductor, said primary of the transformer means being connected to said sheath to capacitively couple with said center conductor.
Claim 24
Dependent Claim
23 words
The circuit of claim 20, wherein said transistor means comprises a mesa transistor, said drive pulse driving the mesa transistor into avalanche mode.
Claim 25
Dependent Claim
157 words
In a method for sampling and holding an analog signal including the steps of: connecting an analog signal to the input of a diode bridge means: applying a turn ''''on'''' voltage greater than the zener voltage of a zener diode means connected in the current pathway of said bridge, to cause conduction between said input of the bridge and a storage capacitor for charging the storage capacitor to the voltage level of the analog signal simultaneously appearing at said input, said zener voltage being greater than the voltage of said analog signal; applying a turn ''''off'''' voltage to bias said bridge and zener diode ''''off'''' whereby said zener voltage maintains the bridge ''''off'''' until said turn ''''on'''' voltage is again applied, and delivering the turn ''''on'''' voltage to the input of an unterminated delay line and deriving a reflected signal from said delay line with a predetermined delay for providing the turn ''''off'''' voltage for said bridge.
Claim 26
Dependent Claim
157 words
In a method for sampling and holding an analog signal including the steps of: connecting an analog signal to the input of a diode bridge means: applying a turn ''''on'''' voltage greater than the zener voltage of a zener diode means connected in the current pathway of said bridge, to cause conduction between said input of the bridge and a storage capacitor for charging the storage capacitor to the voltage level of the analog signal simultaneously appearing at said input, said zener voltage being greater than the voltage of said analog signal; applying a turn ''''off'''' voltage to bias said bridge and zener diode ''''off'''' whereby said zener voltage maintains the bridge ''''off'''' until said turn ''''on'''' voltage is again applied, and delivering the turn ''''on'''' voltage to the input of an unterminated delay line and deriving a reflected signal from said delay line with a predetermined delay for providing the turn ''''off'''' voltage for said bridge.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-09 | 1976-07-10 | 1977-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-09 | 1980-07-10 | 1981-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-09 | 1984-07-10 | 1985-01-09 | $7700.00 | Window Closed / Lapsed |