Differential load circuit equipped with field-effect transistors

Claim 2

A differential load circuit equipped with field-effect transistors of the enhancement type comprises, first and second input terminals and a common terminal, a first and a second field-effect transistor of a first conductivity type having source electrodes connected to the common terminal, gate electrodes interconnected and drain electrodes connected to the first and second input terminals, respectively, a third and a fourth field effect transistor with interconnected gate electrodes, a first and a second current source circuit feeding quiescent currents to the third and the fourth transistor by connecting the drain electrodes of the third and the fourth transistor to the first and the second current source circuit, respectively, means connecting the source electrode of the third and the fourth transistor to the drain electrode of the first and the second transistor, respectively, and means connecting the gate electrodes of the third and fourth transistors to the gate electrodes of the first and the second transistor, at least one first output terminal connected to the drain electrode of the fourth transistor, and biasing means for biasing the gate electrodes of the first, second, third and fourth transistors to a potential such that the third and the fourth transistors carry the quiescent currents supplied by the current source circuits.

Claim 3

A differential load circuit as claimed in claim 1, wherein said biasing means comprise a positive feedback between the drain electrode and the gate electrode of the third transistor.

Claim 4

A differential load circuit as claimed in claim 1, wherein the gate electrodes of the first, second, and third and fourth transistors are connected to a voltage reference source and said biasing means comprise a feed-forward amplifier receiving the common-mode voltage level on the drain electrodes of the third and the fourth transistor and controlling the first and the second current source circuits so that said current source circuits, in respect of the common mode current level, follow the common mode drain current level of the third and the fourth transistor.

Claim 5

A differential load circuit as claimed in claim 1, wherein the biasing means comprise a feed-forward amplifier receiving the common-mode voltage level on the drain electrodes of the third and the fourth transistors and driving the common gate electrodes of the first, second, third and fourth transistors so that the third and the fourth transistors, in respect of the common-mode drain current level, follow the common-mode current level of the first and the second current source circuits.

Claim 6

A differential load circuit as claimed in any one of claims 1-4, which is driven at both input terminals by a first differential amplifier comprising a fifth and a sixth transistor of a second conductivity type opposite to the first conductivity type, said fifth and sixth transistors being connected as a differential pair, with their gate electrodes constituting an input, means connecting the drain electrode of the fifth transistor to the drain electrode of the first transistor and the drain electrode of the sixth transistor to the drain electrode of the second transistor, said first and second current source circuits respectively comprising the series connection of the channels of a seventh and a ninth and of the channels of an eighth and a tenth field-effect transistor of the second conductivity type, the source electrodes of the seventh and the eighth transistor being connected to a second common point and the gate electrodes being interconnected and connected to the gate electrodes of the ninth and the tenth transistor, the drain electrodes of the ninth and the tenth transistors being connected to the drain electrodes of the third and fourth transistors, respectively, and the source electrodes of the ninth and the tenth transistors, respectively, being connected to the drain electrodes of an eleventh and a twelfth field-effect transistor of the first conductivity type having gate electrodes connected to the gate electrodes of the fifth and the sixth transistors, respectively, and having source electrodes connected together.

Claim 7

A differential load circuit as claimed in claim 5, when appendant to claim 2, wherein the gate electrodes of the seventh, eighth, ninth and tenth transistor are connected to the drain electrode of the ninth transistor in a regenerative sense and further comprising a current-sensing element included between the drain electrodes of the third and the ninth transistors.

Claim 8

A differential load circuit as claimed in claim 5, when appendant to claim 3, wherein an output of the feed-forward amplifier is coupled to the commoned gate electrodes of the seventh, eighth, ninth and tenth transistors.

Claim 9

A differential load circuit as claimed in claim 5, when appendant to claim 4, wherein the drain electrodes of the seventh, eighth, ninth and tenth transistors are connected to a voltage reference source.

Claim 10

A differential load circuit as claimed in any one of claims, 1-4 wherein the ratio of the width and length of the channels of the first and second transistors is comparatively small relative to the ratio of the width and length of the channels of the third and fourth transistors.

Claim 11

A differential load circuit as claimed in claim 5 wherein the ratio of the width and the length of the channels of the first, second, seventh and eighth transistors is comparatively small relative to the ratio of the width and length of the channels of the third, fourth, ninth and tenth transistors.

Claim 12

A differential load circuit as claimed in claim 6 wherein the ratio of the width and the length of the channels of the first, second, seventh and eighth transistors is comparatively small relative to the ratio of the width and the length of the channels of the third, fourth, ninth and tenth transistors.

Claim 13

A differential load circuit as claimed in claim 7 wherein the ratio of the width and the length of the channels of the first, second, seventh and eighth transistors is comparatively small relative to the ratio of the width and the length of the channels of the third, fourth, ninth and tenth transistors.

Claim 14

A differential load circuit as claimed in claim 8 wherein the ratio of the width and the length of the channels of the first, second, seventh and eighth transistors is comparatively small relative to the ratio of the width and the length of the channels of the third, fourth, ninth and tenth transistors.

Claim 15

A differential load circuit as claimed in claim 5 wherein the ratio of the width and the length of the channels of the first and second transistors is comparatively small relative to the ratio of the width and length of the channels of the third and fourth transistors.

Claim 16

A differential load circuit comprising, first and second power supply terminals, first, second, third and fourth field-effect transistors of the enhancement type, first and second current source circuits, means connecting the first current source circuit and the first and third transistors in a first series circuit across said supply terminals, means connecting the second current source circuit and the second and fourth transistors in a second series circuit across said supply terminals, first and second input terminals connected to respective junction points between the first and third transistors and the second and fourth transistors, means interconnecting the gate electrodes of the first, second, third and fourth transistors, an output terminal connected to an output electrode of the fourth transistor, and means for biasing the gate electrodes of said transistors to a voltage such that the third and fourth transistors carry quiescent currents supplied by the first and second current source circuits, respectively.

Claim 17

A differential load circuit comprising, first and second power supply terminals, first, second, third and fourth field-effect transistors of the enhancement type, first and second current source circuits, means connecting the first current source circuit and the first and third transistors in a first series circuit across said supply terminals, means connecting the second current source circuit and the second and fourth transistors in a second series circuit across said supply terminals, first and second input terminals connected to respective junction points between the first and third transistors and the second and fourth transistors, means interconnecting the gate electrodes of the first, second, third and fourth transistors, an output terminal connected to an output electrode of the fourth transistor, and means for biasing the gate electrodes of said transistors to a voltage such that the third and fourth transistors carry quiescent currents supplied by the first and second current source circuits, respectively.

Claim 18

A differential load circuit as claimed in claim 15, wherein said biasing means comprises means coupling an output electrode and the gate electrode of the third transistor to provide a positive feedback therebetween.