Circuit for decreasing the effect of parasitic capacitances in field effect transistors used in coupling networks

Claim 1

In a network for selectively coupling each of a plurality of input lines (E1 . . . En) to a plurality of output lines (A1 . . . Am), said coupling network comprising a plurality of field effect transistors each having a source-drain circuit connected between one of said input lines and one of said output lines, a gate terminal and a bulk terminal, said source-drain circuit switching to the conductive state in response to a control signal applied at said gate terminal, thereby providing an output signal on the associated one of said output lines in response to an input signal on the associated one of said input lines, the said output signal being derived from the signal transmitted across the respective source-drain circuit of the FET from the input line to the output line when the said FET is activated by said gate control signal, the improvement comprising means (RV1 . . . RVm) connected to said bulk terminals and at least one of said output lines for applying a compensation signal to said bulk terminals of at least selected ones of said field effect transistors, said compensation signal being derived from said output signal on said at least one output line, and being applied in a form compensating and substantially reducing the effect of parasitic capacitance between said source-drain circuit and said bulk terminals of said field effect transistors.