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US4370729A
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Microprogram sequencer
Assignee: POINT 4 DATA CORP
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Filing: 1980-03-21
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Granted: 1983-01-25
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Expires: 2000-03-21
Abstract
Abstract A microprogram sequencer for generating in a proper sequence the addresses of the successive microinstructions used in executing a given machine instruction includes a PROM next address generator that produces the successive addresses. The successive addresses are utilized as the successive microinstructions. Each address produced includes a normal next address, but this normal next address may be alterable by address alteration signals that are generated in response to a number of sensed conditions within the computer and in response to predetermined machine instruction register bits. The address alteration of a normal next address, if required, is accomplished within the same clock period in which the normal next address is initially formed, permitting jump or branch instructions to be performed as rapidly as normal instructions. No mapping PROM, microsequencer counter, nor microsequencer incrementer are needed to implement the present invention.
Inventors
- 👤 Eugen I. Bosch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 23:56
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/262
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
314 words
A microprogram sequencer for generating in a proper sequence, including required branching, the addresses of the successive microinstructions used in executing a given machine instruction by a computer of the type in which status signals are produced which represent the status of various components of the computer, and in which the operation of the various components is synchronized by a clock which generates a periodic clock signal demarking successively occurring machine cycle clock periods, said microprogram sequencer comprising in combination: address generator memory means for producing during a current machine cycle period a first set of output signals including a first code set of signals designating a normal next input address for said address generator memory means; selector means receiving as inputs applied status signals, instruction signals, and predetermined ones of the set of output signals produced by said address generator memory means, and responsive to the received signals during the current machine cycle period for selectively producing address alteration signals during the current machine cycle period; means for logically combining said address alteration signals and said first code set of signals designating a normal next address during the current machine cycle period to selectively alter the first code set of signals to represent an altered next input address, any alteration of the first code set of signals being established before the end of the current machine cycle period; and means for applying the first code set of signals to said address generator memory means during the current machine cycle period as the input address thereto, said address generator memory means being responsive to such application of the first code set of signals, whether altered or unaltered, for producing during the next successive machine cycle period a selectively corresponding second set of output signals including a second code set of signals designating the next successive normal input address for said address generator memory means.
Claim 2
Dependent Claim
314 words
A microprogram sequencer for generating in a proper sequence, including required branching, the addresses of the successive microinstructions used in executing a given machine instruction by a computer of the type in which status signals are produced which represent the status of various components of the computer, and in which the operation of the various components is synchronized by a clock which generates a periodic clock signal demarking successively occurring machine cycle clock periods, said microprogram sequencer comprising in combination: address generator memory means for producing during a current machine cycle period a first set of output signals including a first code set of signals designating a normal next input address for said address generator memory means; selector means receiving as inputs applied status signals, instruction signals, and predetermined ones of the set of output signals produced by said address generator memory means, and responsive to the received signals during the current machine cycle period for selectively producing address alteration signals during the current machine cycle period; means for logically combining said address alteration signals and said first code set of signals designating a normal next address during the current machine cycle period to selectively alter the first code set of signals to represent an altered next input address, any alteration of the first code set of signals being established before the end of the current machine cycle period; and means for applying the first code set of signals to said address generator memory means during the current machine cycle period as the input address thereto, said address generator memory means being responsive to such application of the first code set of signals, whether altered or unaltered, for producing during the next successive machine cycle period a selectively corresponding second set of output signals including a second code set of signals designating the next successive normal input address for said address generator memory means.
Claim 3
Dependent Claim
72 words
The microprogram sequencer of claim 1 wherein the first code set of signals also designates a corresponding normal microinstruction which is to be executed at the end of the current machine cycle period and wherein any alteration during the current machine cycle period of the first code set of signals to produce an altered next input address also alters the correspondingly designated microinstruction before the end of the current machine cycle period.
Claim 4
Dependent Claim
83 words
The combination of claim 1 wherein said address generator memory means comprises at least one programmable semiconductor memory chip and a semiconductor register for storing the set of output signals including the first code set of signals read out from the memory means, the register presenting at least a predetermined subset of the first code set of signals at open collector outputs thereof, and wherein the selector means comprises semiconductor gating circuitry which produces the address alteration signals at open collector outputs thereof.
Claim 5
Dependent Claim
74 words
The combination of claim 1 wherein the first code set of signals is a set of individual bit signals and the address alteration signals comprise a predetermined plurality of individual address alteration signals corresponding respectively to a predetermined plurality of the bit signals of the first code set of signals, said means for logically combining operating to combine each address alteration signal with the corresponding bit signal to selectively alter the corresponding bit signal.
Claim 6
Dependent Claim
56 words
The combination of claim 4 wherein the address alteration signals comprise four individual address alteration signals corresponding respectively to a predetermined four of the bit signals of the first code set of signals, thereby enabling a sixteen way selectively alterable branch to the next microinstruction address at the end of the current machine operating cycle period.
Claim 7
Dependent Claim
50 words
The combination of claim 1 wherein the first set of output signals includes the first code set of signals and a set of branch control signals, said selector means being responsive to the branch control signals, the applied status signals and instruction signals for selectively producing the address alteration signals.
Claim 8
Independent Claim
185 words
A method of generating during successive machine cycle clock periods in a proper sequence from an addressable microinstruction memory means the corresponding successive microinstructions used in executing a given machine instruction by a computer of the type in which status signals are produced which represent the status of various components of the computer, said method comprising the steps of: (a) during a current machine cycle clock period deriving from the current microinstruction a normal next input address to the microinstruction memory means; (b) generating during the current machine cycle period address alteration signals in response to the status signals and in relation to the machine instruction being executed; (c) combining during the current machine cycle period the address alteration signals with the normal next input address to obtain a selectively altered next input address, any selectively altered next input address being established before the end of the current clock cycle period; and (d) applying the next input address whether altered or unaltered, to the microinstruction memory means during the current machine cycle clock period to select the next successive microinstruction from the microinstruction memory means.
Claim 9
Independent Claim
185 words
A method of generating during successive machine cycle clock periods in a proper sequence from an addressable microinstruction memory means the corresponding successive microinstructions used in executing a given machine instruction by a computer of the type in which status signals are produced which represent the status of various components of the computer, said method comprising the steps of: (a) during a current machine cycle clock period deriving from the current microinstruction a normal next input address to the microinstruction memory means; (b) generating during the current machine cycle period address alteration signals in response to the status signals and in relation to the machine instruction being executed; (c) combining during the current machine cycle period the address alteration signals with the normal next input address to obtain a selectively altered next input address, any selectively altered next input address being established before the end of the current clock cycle period; and (d) applying the next input address whether altered or unaltered, to the microinstruction memory means during the current machine cycle clock period to select the next successive microinstruction from the microinstruction memory means.
References Cited (Backward Citations)
US4155120A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-01-24 | 1986-07-26 | 1987-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-01-24 | 1990-07-26 | 1991-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-01-24 | 1994-07-26 | 1995-01-25 | $7700.00 | Window Closed / Lapsed |