Method of making a monolithic complementary Darlington amplifier utilizing diffusion and epitaxial decomposition

Claim 1

A method of manufacturing a semiconductor device of the type comprising a semiconductor body having at least first and second bipolar and complementary vertical transistors, each transistor comprising a central base region and two external regions serving as emitter and collector regions, said body comprising a substrate covered by a first epitaxial layer of a first conductivity type on which extends a second epitaxial layer of the second conductivity type opposite to the first, the base region of the first transistor and at least a part of an external region of the second transistor being formed by coplanar portions of the first epitaxial layer, the base region of the second transistor and at least a part of an external region of the first transistor being formed by coplanar portions of the second epitaxial layer and a first portion of the substrate comprising at least a part of the collector region of one of said first and second transistors, an insulating barrier separating entirely at least part of said portions of the second epitaxial layer, characterized in that at least a part of the emitter region of the other transistor comprises a second substrate portion of the opposite conductivity type adjoining and coplanar with, and forming a p-n junction with said first portion, that the insulating barrier extends from the upper surface of said second epitaxial layer down to at least the substrate and that said p-n junction comprises at least a part of a junction which extends from the lower surface of the substrate up to said insulating barrier, and that an electrode is provided on the lower surface of the substrate to connect the first and second substrate portions, the method comprising the steps of: providing a semiconductor plate of the first conductivity type and comprising said substrate; locally introducing impurities capable of producing the second conductivity type into at least a portion of said substrate, in a concentration exceeding that of the concentration of impurities in said plate, to form at least a portion of semiconductor material of the second conductivity type in said substrate, the final thickness of said substrate being limited to the thickness of said portion of the second conductivity type; epitaxially growing a lightly-doped first epitaxial layer of a selected conductivity type on a major surface of said substrate; epitaxially growing a lightly-doped second epitaxial layer of opposite conductivity type to that of said selected conductivity type on said first epitaxial layer; forming a plurality of localized semiconductor regions in said second epitaxial layer, including at least first and second localized regions of said selected conductivity type, said first localized region extending through said second epitaxial layer and comprising the base contact of said first transistor, and said second localized region being formed within said second epitaxial layer and comprising an external region of said second transistor; providing said insulating barrier on said second epitaxial layer; and providing said electrode on the lower surface of said substrate.

Claim 2

A method of manufacturing a semiconductor device of the type comprising a semiconductor body having at least first and second bipolar and complementary vertical transistors, each transistor comprising a central base region and two external regions serving as emitter and collector regions, said body comprising a substrate covered by a first epitaxial layer of a first conductivity type on which extends a second epitaxial layer of the second conductivity type opposite to the first, the base region of the first transistor and at least a part of an external region of the second transistor being formed by coplanar portions of the first epitaxial layer, the base region of the second transistor and at least a part of an external region of the first transistor being formed by coplanar portions of the second epitaxial layer and a first portion of the substrate comprising at least a part of the collector region of one of said first and second transistors, an insulating barrier separating entirely at least part of said portions of the second epitaxial layer, characterized in that at least a part of the emitter region of the other transistor comprises a second substrate portion of the opposite conductivity type adjoining and coplanar with, and forming a p-n junction with said first portion, that the insulating barrier extends from the upper surface of said second epitaxial layer down to at least the substrate and that said p-n junction comprises at least a part of a junction which extends from the lower surface of the substrate up to said insulating barrier, and that an electrode is provided on the lower surface of the substrate to connect the first and second substrate portions, the method comprising the steps of: providing a semiconductor plate of the first conductivity type and comprising said substrate; locally introducing impurities capable of producing the second conductivity type into at least a portion of said substrate, in a concentration exceeding that of the concentration of impurities in said plate, to form at least a portion of semiconductor material of the second conductivity type in said substrate, the final thickness of said substrate being limited to the thickness of said portion of the second conductivity type; epitaxially growing a lightly-doped first epitaxial layer of a selected conductivity type on a major surface of said substrate; epitaxially growing a lightly-doped second epitaxial layer of opposite conductivity type to that of said selected conductivity type on said first epitaxial layer; forming a plurality of localized semiconductor regions in said second epitaxial layer, including at least first and second localized regions of said selected conductivity type, said first localized region extending through said second epitaxial layer and comprising the base contact of said first transistor, and said second localized region being formed within said second epitaxial layer and comprising an external region of said second transistor; providing said insulating barrier on said second epitaxial layer; and providing said electrode on the lower surface of said substrate.