Semiconductor memory circuit

Claim 1

A semiconductor memory circuit comprising: memory cells; word lines, hold lines and bit lines connected to respective memory cells; a first constant-current source connected to said hold lines; and a hold-current controlling circuit connected to said first constant-current source; said hold-current controlling circuit comprising: identical controlling circuit elements connected to respective hold lines; and a second constant-current source commonly connected to said identical controlling circuit elements; each of said controlling circuit elements comprising means for absorbing electric charges from a respective hold line when a corresponding word line changes from a selection status to a non-selection status, until the voltage level of the respective hold line reaches a full "L" (low) level or full "H" (high) level and for blocking a flow of electric charges from said respective hold line when said corresponding word line changes from the non-selection status to the selection status, during a predetermined interval after a time data switching from one of said memory cells to another of said memory cells is performed, said blocking and absorbing means comprising: a parallel circuit of a resistor and a capacitor; a transistor having a base connected to said parallel circuit, at a first end, having a first output terminal connected to a respective hold line and having a second output terminal connected to said second constant-current source; a diode connected between said first output terminal and said base of said transistor; and a reference voltage V ref applied to a second end of said parallel circuit.