CMOS Schmitt-trigger circuit

Claim 2

A CMOS Schmitt-trigger circuit for connection between a reference terminal and a power supply terminal and having an input terminal, comprising: a first CMOS inverter operatively connected to said input terminal, comprising a p-channel transistor and a n-channel transistor having an on state resistance, a second CMOS inverter connected in cascade to said first CMOS inverter, a third CMOS inverter connected in cascade to said second CMOS inverter comprising a p-channel transistor and a n-channel transistor, a feedback resistance connected between the output end of said third CMOS inverter and the input end of said second CMOS inverter having a resistance greater than said on state resistance of said n-channel transistor of said first CMOS inverter, and an output terminal connected to the output end of said second inverter for providing an output potential.

Claim 3

A CMOS Schmitt-trigger circuit for connection between a reference terminal and a power supply terminal and having an input terminal, comprising: a first CMOS inverter operatively connected to said input terminal, comprising a p-channel transistor and an n-channel transistor having an on state resistance, a second CMOS inverter connected in cascade to said first CMOS inverter, a third CMOS inverter connected in cascade to said second CMOS inverter comprising a p-channel transistor and a n-channel transistor, a feedback resistance connected between the output end of said third CMOS inverter and the input end of said second CMOS inverter having a resistance greater than said on state resistance of said n-channel transistor of said first CMOS inverter, and an output terminal connected to the output end of said second inverter for providing an output potential; said input terminal receiving an input potential having voltage values reaching both a lower and an upper threshold voltage of the circuit, the difference between said lower and said upper threshold voltages being a predetermined Schmitt width, said output potential varying in response to said input potential, the output end of said first CMOS inverter electrically connected to the input end of said second CMOS inverter, the output end of said second CMOS inverter electrically connected to the input end of said third CMOS inverter, and the output end of said third CMOS inverter electrically connected to the input end of said second CMOS inverter at least when said output potential varies in response to said input potential.

Claim 4

A CMOS Schmitt-trigger circuit for connection between a reference terminal and a power supply terminal and having an input terminal, comprising: a first CMOS inverter operatively connected to said input terminal, comprising a p-channel transistor and an n-channel transistor having an on state resistance, a second CMOS inverter connected in cascade to said first CMOS inverter, a third CMOS inverter connected in cascade to said second CMOS inverter comprising a p-channel transistor and a n-channel transistor, a feedback resistance connected between the output end of said third CMOS inverter and the input end of said second CMOS inverter having a resistance greater than said on state resistance of said n-channel transistor of said first CMOS inverter, and an output terminal connected to the output end of said second inverter for providing an output potential; said input terminal receiving an input potential having voltage values reaching both a lower and an upper threshold voltage of the circuit, the difference between said lower and said upper threshold voltages being a predetermined Schmitt width, said output potential varying in response to said input potential, the output end of said first CMOS inverter electrically connected to the input end of said second CMOS inverter, the output end of said second CMOS inverter electrically connected to the input end of said third CMOS inverter, and the output end of said third CMOS inverter electrically connected to the input end of said second CMOS inverter at least when said output potential varies in response to said input potential.

Claim 5

A CMOS Schmitt-trigger circuit as claimed in claim 1 or 2, wherein said feedback resistance is independent of the voltage at said power supply terminal.

Claim 6

A CMOS Schmitt-trigger circuit as claimed in claim 1 or 2, wherein said feedback resistance is comprised of a p-channel MOS transistor and an n-channel MOS transistor connected in parallel, each respective gate of said MOS transistors being connected to a respective one of said power supply terminal and said reference terminal.

Claim 7

A Schmitt-trigger circuit, comprising: an input terminal; a first inverter comprising at least one transistor, having an on state resistance, and an input and an output, said input thereof being connected to said input terminal; a second inverter comprising an input and an output, said input of said second inverter being operatively connected to said output of said first inverter; a third inverter comprising at least one transistor, having an on state resistance, and an input and an output, said input of said third inverter being operatively connected to said output of said second inverter; a feedback resistor, operatively connected between said output of said third inverter and said input of said second inverter having a resistance greater than said on state resistance of said transistor of said first inverter, and greater than said on state resistance of said transistor of said third inverter; and an output terminal, operatively connected to said output of said second inverter for providing an output potential.

Claim 8

A Schmitt-trigger circuit, comprising: an input terminal; a first inverter comprising at least one transistor, having an on state resistance, and an input and an output, said input thereof being connected to said input terminal; a second inverter comprising an input and an output, said input of said second inverter being operatively connected to said output of said first inverter; a third inverter comprising at least one transistor, having an on state resistance, and an input and an output, said input of said third inverter being operatively connected to said output of said second inverter; a feedback resistor, operatively connected between said output of said third inverter and said input of said second inverter having a resistance greater than said on state resistance of said transistor of said first inverter, and greater than said on state resistance of said transistor of said third inverter; and an output terminal, operatively connected to said output of said second inverter for providing an output potential.

Claim 9

A Schmitt-trigger circuit, comprising: an input terminal; a first inverter comprising at least one transistor, having an on state resistance, and an input and an output, said input thereof being connected to said input terminal; a second inverter comprising an input and an output, said input of said second inverter being operatively connected to said output of said first inverter; a third inverter comprising at least one transistor having an on state resistance, and an input and an output, said input of said third inverter being operatively connected to said output of said second inverter; a feedback resistor, operatively connected between said output of said third inverter and said input of said second inverter having a resistance greater than said on state resistance of said transistor of said first inverter, and greater than said on state resistance of said transistor of said third inverter; and an output terminal, operatively connected to said output of said second inverter for providing an output potential; said input terminal receiving an input potential having voltage values reaching both a lower and an upper threshold voltage of the circuit, the difference between said lower and upper threshold voltages being a predetermined Schmitt width, said output potential varying in response to said input potential; the output end of said first inverter electrically connected to the input end of said second inverter, the output end of said second inverter electrically connected to the input end of said third inverter, and the output end of said third inverter electrically connected to the input end of said second inverter at least when said output potential varies in response to said input potential.

Claim 10

A Schmitt-trigger circuit, comprising: an input terminal; a first inverter comprising at least one transistor, having an on state resistance, and an input and an output, said input thereof being connected to said input terminal; a second inverter comprising an input and an output, said input of said second inverter being operatively connected to said output of said first inverter; a third inverter comprising at least one transistor having an on state resistance, and an input and an output, said input of said third inverter being operatively connected to said output of said second inverter; a feedback resistor, operatively connected between said output of said third inverter and said input of said second inverter having a resistance greater than said on state resistance of said transistor of said first inverter, and greater than said on state resistance of said transistor of said third inverter; and an output terminal, operatively connected to said output of said second inverter for providing an output potential; said input terminal receiving an input potential having voltage values reaching both a lower and an upper threshold voltage of the circuit, the difference between said lower and upper threshold voltages being a predetermined Schmitt width, said output potential varying in response to said input potential; the output end of said first inverter electrically connected to the input end of said second inverter, the output end of said second inverter electrically connected to the input end of said third inverter, and the output end of said third inverter electrically connected to the input end of said second inverter at least when said output potential varies in response to said input potential.

Claim 11

The circuit of claim 5 or 6, wherein said respective inverters comprise CMOS devices.

Claim 12

The circuit of claim 7, further comprising means for receiving power supply and ground voltages, and wherein each of said inverters comprises: first and second MOS transistors connected in series between the power supply voltage and the ground voltage, said first and second transistors each respectively comprising a gate; said input of said respective inverter being connected to both of said respective gates of said first and second MOS transistors; said output of said respective inverter being connected between said first and second transistors; and wherein said first and second transistors are of mutually opposite conduction types.

Claim 13

A schmitt-trigger circuit, comprising: an input terminal; a first inverter comprising at least one transistor, having an on state resistance, and an input and an output, said input thereof being connected to said input terminal; a second inverter comprising an input and an output, said input of said second inverter being operatively connected to said output of said first inverter; a third inverter comprising at least one transistor, having an on state resistance, and an input and an output, said input of said third inverter being operatively connected to said output of said second inverter; a resistance element, operatively connected between said output of said third inverter and said input of said second inverter having a resistance greater than said on state resistance of said transistor of said first inverter, and greater than said on state resistance of said transistor of said third inverter; and an output terminal, operatively connected to said output of said second inverter for providing an output potential.

Claim 14

A schmitt-trigger circuit, comprising: an input terminal; a first inverter comprising at least one transistor, having an on state resistance, and an input and an output, said input thereof being connected to said input terminal; a second inverter comprising an input and an output, said input of said second inverter being operatively connected to said output of said first inverter; a third inverter comprising at least one transistor, having an on state resistance, and an input and an output, said input of said third inverter being operatively connected to said output of said second inverter; a resistance element, operatively connected between said output of said third inverter and said input of said second inverter having a resistance greater than said on state resistance of said transistor of said first inverter, and greater than said on state resistance of said transistor of said third inverter; and an output terminal, operatively connected to said output of said second inverter for providing an output potential.

Claim 15

A schmitt-trigger circuit, comprising: an input terminal; a first inverter comprising at least one transistor, having an on state resistance, and an input and an output, said input thereof being connected to said input terminal; a second inverter comprising an input and an output, said input of said second inverter being operatively connected to said output of said first inverter; a third inverter comprising at least one transistor, having an on state resistance, and an input and an output, said input of said third inverter being operatively connected to said output of said second inverter; a resistance element, operatively connected between said output of said third inverter and said input of said second inverter having a resistance greater than said on state resistance of said transistor of said first inverter, and greater than said on state resistance of said transistor of said third inverter; and an output terminal, operatively connected to said output of said second inverter for providing an output potential; said input terminal receiving an input potential having voltage values reaching both a lower and an upper threshold voltage of the circuit, the difference between said lower and upper threshold voltages being a predetermined Schmitt width, said output potential varying in response to said input potential; the output end of said first inverter electrically connected to the input end of said second inverter, the output end of said second inverter electrically connected to the input end of said third inverter, and the output end of said third inverter electrically connected to the input end of said second inverter at least when said output potential varies in response to said input potential.

Claim 16

A schmitt-trigger circuit, comprising: an input terminal; a first inverter comprising at least one transistor, having an on state resistance, and an input and an output, said input thereof being connected to said input terminal; a second inverter comprising an input and an output, said input of said second inverter being operatively connected to said output of said first inverter; a third inverter comprising at least one transistor, having an on state resistance, and an input and an output, said input of said third inverter being operatively connected to said output of said second inverter; a resistance element, operatively connected between said output of said third inverter and said input of said second inverter having a resistance greater than said on state resistance of said transistor of said first inverter, and greater than said on state resistance of said transistor of said third inverter; and an output terminal, operatively connected to said output of said second inverter for providing an output potential; said input terminal receiving an input potential having voltage values reaching both a lower and an upper threshold voltage of the circuit, the difference between said lower and upper threshold voltages being a predetermined Schmitt width, said output potential varying in response to said input potential; the output end of said first inverter electrically connected to the input end of said second inverter, the output end of said second inverter electrically connected to the input end of said third inverter, and the output end of said third inverter electrically connected to the input end of said second inverter at least when said output potential varies in response to said input potential.

Claim 17

The circuit of claim 9 or 10, further comprising means for receiving a power supply voltage and a ground voltage, and wherein said resistance element further comprises an active component controlled by the power supply voltage.

Claim 18

The circuit of claim 11, wherein said resistance element comprises first and second MOS transistors connected in parallel between said output of said third inverter and said input of said second inverter, said first and second transistors being of complementary conduction types.

Claim 19

The circuit of claim 12, wherein said first MOS transistor is a p-channel transistor and further comprises a gate connected to the ground voltage, and wherein said second MOS transistor is a n-channel transistor and further comprises a gate connected to the power supply voltage.

Claim 20

The circuit of claim 13, wherein each of said inverters respectively comprises: third and fourth MOS transistors connected in series between the power supply voltage and the ground voltage, said third and fourth transistors each respectively also comprising a gate; said input of said respective inverter being connected to both said respective gates of said third and fourth MOS transistors; said output of said respective inverter being provided from a connection point between said third and fourth transistors; and wherein said third and fourth transistors are of mutually opposite conduction types.