US4366556A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Mitsubishi Electric Corp
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Filing: 1980-03-31
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Granted: 1982-12-28
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Expires: 2000-03-31
Abstract
Abstract A memory cell formed of two serially connected MOS transistors one of which has a floating gate is connected to a series combination of a Y address MOS transistor, a readout selection MOS transistor and an MOS transistor disposed in an output buffer circuit across two DC sources. A writing selection MOS transistor is connected across the series combination of the last-mentioned two transistors. The Y address MOS transistor, the readout selection MOS transistor, the output buffer MOS transistor and the writing selection MOS transistor are all operated in the triode region with V G -V TH >V D and at least one of these MOS transistors has a channel conductivity type different from the channel conductivity type of the memory cell MOS transistors.
Inventors
- 👤 Mikio Kyomasu
- 👤 Yoshiharu Nakao
- 👤 Mitsuo Nakayama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:00
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/04; G11C16/0408; G11C16/0433; G11C17/00; G11C17/08; G11C17/10; G11C17/12; H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/858
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
209 words
A semiconductor memory device comprising: a memory cell including a memory element formed of a MOS transistor for performing a storing operation by accumulating an electric charge on an electrically insulating film; a gate circuit including a MOS transistor serially connected to said memory cell; a readout selection circuit including a MOS transistor serially connected to said MOS transistor included in said gate circuit; an output buffer circuit including a MOS transistor connected to said MOS transistor included in said readout selection circuit; a writing selection circuit including a MOS transistor connected in a parallel circuit relationship with said MOS transistors included in said readout selection circuit and said output buffer circuit; and a voltage source system connected to said memory cell, said gate circuit, said writing selection circuit, said readout selection circuit and said output buffer circuit for applying voltages to each of said MOS transistors to satify the relationship V G -V TH >V D for each of said MOS transistors, wherein V G designates the gate voltage, V TH designates the threshold voltage and V D designates the drain voltage; the conductivity type of said MOS transistors included in said gate circuit being different from the conductivity type of said MOS transistor forming said memory element.
Claim 2
Dependent Claim
209 words
A semiconductor memory device comprising: a memory cell including a memory element formed of a MOS transistor for performing a storing operation by accumulating an electric charge on an electrically insulating film; a gate circuit including a MOS transistor serially connected to said memory cell; a readout selection circuit including a MOS transistor serially connected to said MOS transistor included in said gate circuit; an output buffer circuit including a MOS transistor connected to said MOS transistor included in said readout selection circuit; a writing selection circuit including a MOS transistor connected in a parallel circuit relationship with said MOS transistors included in said readout selection circuit and said output buffer circuit; and a voltage source system connected to said memory cell, said gate circuit, said writing selection circuit, said readout selection circuit and said output buffer circuit for applying voltages to each of said MOS transistors to satify the relationship V G -V TH >V D for each of said MOS transistors, wherein V G designates the gate voltage, V TH designates the threshold voltage and V D designates the drain voltage; the conductivity type of said MOS transistors included in said gate circuit being different from the conductivity type of said MOS transistor forming said memory element.
Claim 3
Dependent Claim
210 words
A semiconductor memory device comprising: a memory cell including a memory element formed of a MOS transistor for performing a storing operation by accumulating an electric charge on an electrically insulating film; a gate circuit including a MOS transistor serially connected to said memory cell; a readout selection circuit including a MOS transistor serially connected to said MOS transistor included in said gate circuit; an output buffer circuit including a MOS transistor connected to said MOS transistor included in said readout selection circuit; a writing selection circuit including a MOS transistor connected in a parallel circuit relationship with said MOS transistors included in said readout selection circuit and said output buffer circuit; and a voltage source system connected to said memory cell, said gate circuit, said writing selection circuit, said readout selection circuit and said output buffer circuit for applying voltages to each of said MOS transistors to satisfy the relationship V G -V TH >V D for each of said MOS transistors, wherein V G designates the gate voltage, V TH designates the threshold voltage and V D designates the drain voltage; the conductivity type of said MOS transistors included in said writing selection circuit being different from the conductivity type of said MOS transistor forming said memory element.
Claim 4
Dependent Claim
210 words
A semiconductor memory device comprising: a memory cell including a memory element formed of a MOS transistor for performing a storing operation by accumulating an electric charge on an electrically insulating film; a gate circuit including a MOS transistor serially connected to said memory cell; a readout selection circuit including a MOS transistor serially connected to said MOS transistor included in said gate circuit; an output buffer circuit including a MOS transistor connected to said MOS transistor included in said readout selection circuit; a writing selection circuit including a MOS transistor connected in a parallel circuit relationship with said MOS transistors included in said readout selection circuit and said output buffer circuit; and a voltage source system connected to said memory cell, said gate circuit, said writing selection circuit, said readout selection circuit and said output buffer circuit for applying voltages to each of said MOS transistors to satisfy the relationship V G -V TH >V D for each of said MOS transistors, wherein V G designates the gate voltage, V TH designates the threshold voltage and V D designates the drain voltage; the conductivity type of said MOS transistors included in said writing selection circuit being different from the conductivity type of said MOS transistor forming said memory element.
Claim 5
Dependent Claim
210 words
A semiconductor memory device comprising: a memory cell including a memory element formed of a MOS transistor for performing a storing operation by accumulating an electric charge on an electrically insulating film; a gate circuit including a MOS transistor serially connected to said memory cell; a readout selection circuit including a MOS transistor serially connected to said MOS transistor included in said gate circuit; an output buffer circuit including a MOS transistor connected to said MOS transistor included in said readout selection circuit; a writing selection circuit including a MOS transistor connected in a parallel circuit relationship with said MOS transistors included in said readout selection circuit and said output buffer circuit; and a voltage source system connected to said memory cell, said gate circuit, said writing selection circuit; said readout selection circuit and said output buffer circuit for applying voltages to each of said MOS transistors to satisfy the relationship V G -V TH >V D for each of said MOS transistors, wherein V G designates the gate voltage, V TH designates the threshold voltage and V D designates the drain voltage; the conductivity type of said MOS transistors included in said readout selection circuit being different from the conductivity type of said MOS transistor forming said memory element.
Claim 6
Dependent Claim
210 words
A semiconductor memory device comprising: a memory cell including a memory element formed of a MOS transistor for performing a storing operation by accumulating an electric charge on an electrically insulating film; a gate circuit including a MOS transistor serially connected to said memory cell; a readout selection circuit including a MOS transistor serially connected to said MOS transistor included in said gate circuit; an output buffer circuit including a MOS transistor connected to said MOS transistor included in said readout selection circuit; a writing selection circuit including a MOS transistor connected in a parallel circuit relationship with said MOS transistors included in said readout selection circuit and said output buffer circuit; and a voltage source system connected to said memory cell, said gate circuit, said writing selection circuit; said readout selection circuit and said output buffer circuit for applying voltages to each of said MOS transistors to satisfy the relationship V G -V TH >V D for each of said MOS transistors, wherein V G designates the gate voltage, V TH designates the threshold voltage and V D designates the drain voltage; the conductivity type of said MOS transistors included in said readout selection circuit being different from the conductivity type of said MOS transistor forming said memory element.
Claim 7
Dependent Claim
210 words
A semiconductor memory device comprising: a memory cell including a memory element formed of a MOS transistor for performing a storing operation by accumulating an electric charge on an electrically insulating film; a gate circuit including a MOS transistor serially connected to said memory cell; a readout selection circuit including a MOS transistor serially connected to said MOS transistor included in said gate circuit; an output buffer circuit including a MOS transistor connected to said MOS transistor included in said readout selection circuit; a writing selection circuit including a MOS transistor connected in a parallel circuit relationship with said MOS transistors included in said readout selection circuit and said output buffer circuit; and a voltage source system connected to said memory cell, said gate circuit, said writing selection circuit, said readout selection circuit and said output buffer circuit for applying voltages to each of said MOS transistors to satisfy the relationship V G -V TH >V D for each of said MOS transistors, wherein V G designates the gate voltage, V TH designates the threshold voltage and V D designates the drain voltage; the conductivity type of said MOS transistors included in said output buffer circuit being different from the conductivity type of said MOS transistor forming said memory element.
Claim 8
Dependent Claim
210 words
A semiconductor memory device comprising: a memory cell including a memory element formed of a MOS transistor for performing a storing operation by accumulating an electric charge on an electrically insulating film; a gate circuit including a MOS transistor serially connected to said memory cell; a readout selection circuit including a MOS transistor serially connected to said MOS transistor included in said gate circuit; an output buffer circuit including a MOS transistor connected to said MOS transistor included in said readout selection circuit; a writing selection circuit including a MOS transistor connected in a parallel circuit relationship with said MOS transistors included in said readout selection circuit and said output buffer circuit; and a voltage source system connected to said memory cell, said gate circuit, said writing selection circuit, said readout selection circuit and said output buffer circuit for applying voltages to each of said MOS transistors to satisfy the relationship V G -V TH >V D for each of said MOS transistors, wherein V G designates the gate voltage, V TH designates the threshold voltage and V D designates the drain voltage; the conductivity type of said MOS transistors included in said output buffer circuit being different from the conductivity type of said MOS transistor forming said memory element.
Claim 9
Dependent Claim
31 words
A semiconductor memory device as claimed in claims 1 or 2 or 3 or 4, wherein said writing selection circuit and said readout selection circuit are formed of complementary MOS transistors.
Claim 10
Dependent Claim
27 words
A semiconductor memory device as claimed in claims 1 or 2 or 3 or 4, wherein said memory element is formed of a p channel MOS transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-12-27 | 1986-06-28 | 1986-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-12-27 | 1990-06-28 | 1990-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-12-27 | 1994-06-28 | 1994-12-28 | $7700.00 | Window Closed / Lapsed |