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US4366555A
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Electrically erasable programmable read only memory
Assignee: National Semiconductor Corp
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Filing: 1980-08-01
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Granted: 1982-12-28
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Expires: 2000-08-01
Abstract
Abstract An Electrically Erasable Programmable Read-Only Memory (EEPROM) requires only a single voltage applied to a single control gate for both erasing and writing operations. Writing is accomplished by hot channel electron injection to charge the floating gate of a selected device with electrons. Nonselected devices are kept from charging by either floating their sources or grounding their gates. Devices are erased by grounding the source and drain regions and causing the electrons stored in the floating gates to tunnel to the control gate. Preferred ratioing of the intra-device capacitances prevents erasure of nonselected devices during writing.
Inventors
- 👤 Chenming Hu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:24
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; G11C16/06; G11C16/08; G11C16/10; G11C16/14; G11C16/26; G11C16/30
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
106 words
An EEPROM memory array of floating gate field effect semiconductor devices, each device having a floating gate and a control gate modulating conduction in a channel between source and drain regions, the devices organized in a matrix of columns and rows, the sources of devices on each column coupled to a common column conductor, the control gates of devices on each row coupled to a common row conductor, and the drains of all devices coupled to a common drain conductor, the array further comprising: means for sensing conduction in the semiconductor devices; and means for selectively floating common column conductors so as to program the array.
Claim 2
Dependent Claim
106 words
An EEPROM memory array of floating gate field effect semiconductor devices, each device having a floating gate and a control gate modulating conduction in a channel between source and drain regions, the devices organized in a matrix of columns and rows, the sources of devices on each column coupled to a common column conductor, the control gates of devices on each row coupled to a common row conductor, and the drains of all devices coupled to a common drain conductor, the array further comprising: means for sensing conduction in the semiconductor devices; and means for selectively floating common column conductors so as to program the array.
Claim 3
Dependent Claim
27 words
An EEPROM memory array as in claim 1 wherein the means for sensing conduction comprises a current detector selectively coupled to one of the common column conductors.
Claim 4
Dependent Claim
19 words
The array of claim 1 including means to apply a positive voltage to said common drain conductor during programming.
Claim 5
Dependent Claim
40 words
The array of claim 1 in which said means for selectively floating common column conductors comprises means to ground the column conductor for the column containing the selected device to be programmed and means to float all other column conductors.
Claim 6
Dependent Claim
19 words
The array of claim 4 including means to apply a positive voltage to said common drain conductor during programming.
Claim 7
Dependent Claim
30 words
An array as in claim 1 further comprising means for selectively applying either a first voltage or a ground voltage to the common drain conductor for programming or reading respectively.
Claim 8
Dependent Claim
66 words
An EEPROM memory array as in claim 6 further comprising means for selectively applying either a second, third or a ground voltage to each common row conductor, and a fourth or a ground voltage to the common column conductors, the second voltage being greater than the first voltage, the third voltage less than one-half the second voltage, and the fourth voltage less than the third voltage.
Claim 9
Dependent Claim
38 words
An EEPROM memory array as in claim 7 wherein the first voltage is approximately 17 volts, the second voltage is approximately 25 volts, the third voltage is approximately 5 volts and the fourth voltage is approximately 2 volts.
Claim 10
Dependent Claim
24 words
An EEPROM memory array as in claim 1 wherein the means for sensing conduction comprises a current detector coupled to the common drain conductor.
Claim 11
Dependent Claim
27 words
An EEPROM memory array as in claims 1 or 9 wherein the source-to-floating gate capacitance, the floating gate-to-channel capacitance and the floating gate-to-drain capacitance are approximately equal.
Claim 12
Dependent Claim
38 words
An EEPROM memory array as in claim 10 wherein the floating gate-to-control gate capacitance is approximately equal to the sum of the capacitances between the source and floating gate, channel and floating gate, and drain and floating gate.
Claim 13
Dependent Claim
15 words
An EEPROM memory array as in claim 11 wherein the semiconductor devices are n-channel devices.
Claim 14
Independent Claim
191 words
A method for operating an EEPROM memory array of the type having floating gate field effect semiconductor devices arranged in rows and columns with the sources of devices in each column coupled to a common column conductor and the control gates of the devices in each row coupled to a common row conductor and all the drains connecting to a common drain; the method comprising the steps of: charging a selected device by applying a first voltage to the common drain, applying a second voltage to the common row conductor of the selected device, applying a ground voltage to the other common row conductors, applying a ground voltage to the common column conductor of the selected device, and floating the other common column conductors; reading the selected device by applying a third voltage to the common row conductor of the selected device, applying a fourth voltage between the common source conductor and the drain of the selected device, and detecting the current flowing through the selected device, and erasing the selected device by applying the second voltage to the control gate and applying the ground voltage to the drain and source.
Claim 15
Independent Claim
191 words
A method for operating an EEPROM memory array of the type having floating gate field effect semiconductor devices arranged in rows and columns with the sources of devices in each column coupled to a common column conductor and the control gates of the devices in each row coupled to a common row conductor and all the drains connecting to a common drain; the method comprising the steps of: charging a selected device by applying a first voltage to the common drain, applying a second voltage to the common row conductor of the selected device, applying a ground voltage to the other common row conductors, applying a ground voltage to the common column conductor of the selected device, and floating the other common column conductors; reading the selected device by applying a third voltage to the common row conductor of the selected device, applying a fourth voltage between the common source conductor and the drain of the selected device, and detecting the current flowing through the selected device, and erasing the selected device by applying the second voltage to the control gate and applying the ground voltage to the drain and source.
Claim 16
Dependent Claim
36 words
A method as in claim 13 wherein the second voltage is greater than the first voltage, the third voltage is less than one-half the second voltage, and the fourth voltage is less than the third voltage.
Claim 17
Dependent Claim
36 words
A method as in claim 14 wherein the first voltage is approximately 17 volts, the second voltage is approximately 25 volts, the third voltage is approximately 5 volts, and the fourth voltage is approximately 2 volts.
References Cited (Backward Citations)
US4282446A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-12-27 | 1986-06-28 | 1986-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-12-27 | 1990-06-28 | 1990-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-12-27 | 1994-06-28 | 1994-12-28 | $7700.00 | Window Closed / Lapsed |