Modular signal-processing system

Claim 1

An electronic signal-processing system dialoguing with associated peripheral units, comprising: a plurality of modular processing units each including a pair of substantially identical microprocessors interlinked by a correlating connection, each microprocessor being provided with parallel input connections for receiving incoming messages from an internal signal path, only one of said microprocessors having an active output connection for transmitting outgoing messages to said signal path, the other of said microprocessors being available as a standby, each processing unit further including interface means inserted between said signal path and an associated one of said peripheral units, an internal memory connected to said signal path for storing processing information individual to the associated peripheral unit, and coupling means for selectively connecting said signal path to any one of a plurality of external two-way buses forming extensions of said signal path; a plurality of external memory banks storing general processing information utilizable by any of said processing units; and access means individual to each of said memory banks for facilitating communication thereof with any of said processing units, in response to a request therefrom, via a corresponding one of said external two-way buses; each microprocessor of said pair including logical circuitry for performing processing operations, a microprogram memory connected to said logical circuitry for controlling said processing operations, a sequencer linked to said microprogram memory for advancing the microprogram thereof by the emission of addresses of microinstructions to be successively read out therefrom, a time base connected to said logical circuitry and said sequencer for generating a control pulse to establish an operating cycle therefor, and monitoring means in each microprocessor operatively connected to the sequencers of both microprocessors of said pair via said correlating connection and being further connected to said time base for causing same to lengthen the control pulse thereof to double the normal duration of said operating cycle upon detecting an out-of-step condition of said sequencers, thereby enabling resynchronization of said microprocessors upon termination of said out-of-step condition after not more than one normal operating cycle, said one of said microprocessors having said logical circuitry linked with said signal path via said active output connection for sending out the results of said processing operations.