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US4365312A
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Sequence controller
Assignee: Mitsubishi Electric Corp
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Filing: 1979-08-30
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Granted: 1982-12-21
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Expires: 1999-08-30
Abstract
Abstract A sequence controller having a memory for storing predetermined control sequences, an operation device for sequentially reading the contents of the memory and executing the control sequences stored therein in accordance with externally supplied instructions, a programming panel for reading and displaying data from the memory and for writing the control sequence in the memory, bus lines coupled to the operation device and the panel, respectively, to permit parallel operation thereof without lowering the processing speed and to permit programming of the operation device without using conventional input-output instructions by supplying input and output data for operating an external controlled process from the operation device via an output memory.
Inventors
- 👤 Nobumasa Nakano
- 👤 Noboru Takahashi
- 👤 Masao Aoki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:31
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/05; G05B19/054; G05B2219/00; G05B2219/10; G05B2219/11; G05B2219/1103; G05B2219/1159; G05B2219/15; G05B2219/15048
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
455 words
A sequence controller comprising: a first memory for storing data representing a series of predetermined sequence control steps; a first processing unit for reading out the data representing the series of sequence control steps stored in the first memory and for controlling execution of the sequence control steps; a second memory for temporarily storing data for execution of sequence control steps when execution of said steps is being performed by the first processing unit; a second processing unit comprising at least one of means for reading and displaying at least portions of the data stored in the first memory, means for converting externally supplied sequence control information data into a predetermined format and writing the data in the format into the first memory, and means for reading and displaying the temporarily stored data in the second memory; a third memory having an input memory portion and an output memory portion, the output memory portion storing output information data from the first processing unit produced in response to execution by the first processing unit of the sequence control steps and the input memory portion storing information representing parameters of an externally controlled process; means for operating the externally controlled process in response to the output information data stored in the third memory; a third processing unit, said third processing unit comprising means for determining when the first processing unit is not accessing the third memory, means for sequentially reading out the output information data stored in the output memory portion and transferring the output information data to the means for operating the externally controlled process, and means for sequentially writing data representing the parameters of the externally controlled process into the input memory portion, the reading and transferring means and the writing means being operative when and only when the determining means indicates that the first processing unit is not accessing the third memory unit; first, second and third switching gates coupled to the first, second and third memories, respectively, the first and second switching gates being responsive only to read/write requests suppled randomly from the first and second processing units for transferring data between the first and second memories and the first and second processing units, and said third switching gate being responsive only to read/write requests supplied from the first processing device and the third processing device for transferring data between the third memory and the first and third processing devices, respectively; and first and second read/write control lines coupled to the first and second processing units, respectively, and to the first, second and third switching gates for selectively coupling the first and second processing units to the first, second and third memories, the first and second read/write lines operating independently of one another.
Claim 2
Dependent Claim
455 words
A sequence controller comprising: a first memory for storing data representing a series of predetermined sequence control steps; a first processing unit for reading out the data representing the series of sequence control steps stored in the first memory and for controlling execution of the sequence control steps; a second memory for temporarily storing data for execution of sequence control steps when execution of said steps is being performed by the first processing unit; a second processing unit comprising at least one of means for reading and displaying at least portions of the data stored in the first memory, means for converting externally supplied sequence control information data into a predetermined format and writing the data in the format into the first memory, and means for reading and displaying the temporarily stored data in the second memory; a third memory having an input memory portion and an output memory portion, the output memory portion storing output information data from the first processing unit produced in response to execution by the first processing unit of the sequence control steps and the input memory portion storing information representing parameters of an externally controlled process; means for operating the externally controlled process in response to the output information data stored in the third memory; a third processing unit, said third processing unit comprising means for determining when the first processing unit is not accessing the third memory, means for sequentially reading out the output information data stored in the output memory portion and transferring the output information data to the means for operating the externally controlled process, and means for sequentially writing data representing the parameters of the externally controlled process into the input memory portion, the reading and transferring means and the writing means being operative when and only when the determining means indicates that the first processing unit is not accessing the third memory unit; first, second and third switching gates coupled to the first, second and third memories, respectively, the first and second switching gates being responsive only to read/write requests suppled randomly from the first and second processing units for transferring data between the first and second memories and the first and second processing units, and said third switching gate being responsive only to read/write requests supplied from the first processing device and the third processing device for transferring data between the third memory and the first and third processing devices, respectively; and first and second read/write control lines coupled to the first and second processing units, respectively, and to the first, second and third switching gates for selectively coupling the first and second processing units to the first, second and third memories, the first and second read/write lines operating independently of one another.
Claim 3
Dependent Claim
64 words
The sequence controller of claim 1, wherein the capacities of the input and output memory portions are larger than a maximum number of input data points, corresponding to the information representing the parameters of the externally controlled process, and a maximum number of output data points, corresponding to said output information data, required for operating the externally controlled process operated by the corresponding controller.
Claim 4
Dependent Claim
52 words
The sequence controller of claim 1 further comprising first and second answer back lines corresponding to said first and second read/write lines, respectively, said first and second processing units producing answer back signals on the first and second answer back lines, respectively, in response to read/write signals on the corresponding read/write line.
Claim 5
Dependent Claim
85 words
The sequence controller of claim 2, wherein the third processing unit comprises a counter having a count capacity larger than a sum of the maximum number of input data points and the maximum number of output data points, outputs of said counter being coupled as an address to the third switching gate and the means for operating the externally controlled process and means for producing clock pulses for operating said counter only when said third memory is not being accessed by said first processing unit.
Claim 6
Dependent Claim
15 words
The sequence controller of claim 1 wherein the first processing unit comprises a microcomputer chip.
Claim 7
Dependent Claim
21 words
The sequence controller of claim 1 wherein the second processing unit comprises a programming panel having a keyboard and displaying means.
Claim 8
Dependent Claim
30 words
The sequence controller of claim 1 wherein the second processing unit comprises a process computer for monitoring the operation of the first processing unit and for revising a sequence program.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-12-20 | 1986-06-21 | 1986-12-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-12-20 | 1990-06-21 | 1990-12-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-12-20 | 1994-06-21 | 1994-12-21 | $7700.00 | Window Closed / Lapsed |