Multi-layered metallized silicon matrix substrate

Claim 2

A substrate having a coefficient of expansion in the range of 2.5×10 -6 to 4.1×10 -6 °K -1 comprising a matrix of sintered silicon particles of a size less than 5 microns, each particle joined and surrounded by an electrically insulating layer of a silicon compound selected from the group consisting of silicon dioxide, silicon nitride, and mixtures thereof, said insulating layer of a thickness in the range of 0.1 to 1 micron, said substrate including conductor lines formed therein, and having electrical connection pads on a surface thereof.

Claim 3

The substrate of claim 1 wherein the silicon particles have a size range of about 1 to 3 microns, and the substrate has a coefficient of expansion of about 4.1×10 -6 °K -1 , a thermal conductivity of about 0.2 Cal S -1 Cm -1 °K -1 , and a dielectric constant range of about 5 to 7.

Claim 4

An integrated circuit module with at least one silicon semiconductor integrated circuit chip having electric conductors on a surface thereof, and a multi-layer laminated substrate having a coefficient of expansion in the range of 2.5×10 -6 to 4.1 ×10 -6 °K -1 comprising, a matrix of sintered silicon particles of a size less than 5 microns, each particle joined and surrounded by an insulating layer of a silicon compound selected from the group consisting of silicon dioxide, silicon nitride, and mixtures thereof, said insulating layer of a thickness in the range of 0.1 to 1 micron, said substrate having conductor lines formed therein and having electrical connection pads at a surface thereof, said electrical conductors and said pads being bonded together to form an electrically connected unitary structure.

Claim 5

An integrated circuit module with at least one silicon semiconductor integrated circuit chip having electric conductors on a surface thereof, and a multi-layer laminated substrate having a coefficient of expansion in the range of 2.5×10 -6 to 4.1 ×10 -6 °K -1 comprising, a matrix of sintered silicon particles of a size less than 5 microns, each particle joined and surrounded by an insulating layer of a silicon compound selected from the group consisting of silicon dioxide, silicon nitride, and mixtures thereof, said insulating layer of a thickness in the range of 0.1 to 1 micron, said substrate having conductor lines formed therein and having electrical connection pads at a surface thereof, said electrical conductors and said pads being bonded together to form an electrically connected unitary structure.

Claim 6

The module of claim 3 wherein the silicon particles have a size range of about 1 to 3 microns, the substrate has a coefficient of expansion of about 4.1×10 -6 °K -1 , a thermal conductivity of about 0.2 Cal S -1 Cm -1 °K -1 , and a dielectric constant range of about 5 to 7.

Claim 7

The module of claim 3 wherein the surfaces of the chip and the substrate are bonded together in face-to-face relationship with an insulating layer.