Digital-to-analog converter useful in a television receiver

Claim 1

In a system including register means for storing a plurality of N bits representing in combination the magnitude of an analog signal, each of said bits having a respective identifying number n between N and 1 and representing a respective power of 2 equal to 2 n-1 , each of said bits having either a first or a second level indicating the presence or absence, respectively, of said bit in the combination representing said magnitude, apparatus for converting the contents of said register means to a pulse signal having, in general, G pulses representing the magnitude of said analog signal, comprising: clock means for generating clock pulses; counter means for generating a plurality of binary pulse signals in response to said clock pulses, each of said binary pulse signals having pulses with durations proportional to a respective power of 2; a plurality of N selection AND gate means each having an identifying number n between N and 1, each of said selection means being responsive to a respectively numbered bit and a respective predetermined one of said binary pulse signals for selecting pulses from the respective predetermined binary pulse signal to derive a respectively numbered output pulse signal when said respectively numbered bit has said first level; each of said selection AND gate means which has an identifying number n between N and M+1, where M is a positive integer greater than zero and 2 M is equal to G, being responsive to the one of said binary pulse signals having pulses with durations corresponding to ##EQU8## each of said selection AND gate means which has an identifying number n equal to or less than M being responsive to the one of said binary pulse signals having pulses with durations corresponding to 2 N-n ; said selection AND gate means which has the identifying number N selecting all of the pulses of the respective predetermined binary pulse signal to derive the respectively numbered output pulse signal having G pulses when the respectively numbered bit has the first level; a plurality of position determining means each having an identifying number between N-1 and 1, each of said position determining means generating a respectively numbered position determining pulse signal having pulses which occur substantially in coincidence with the time intervals not occupied by pulses of all the preceding higher numbered output pulse signals; each of said selection AND gate means which has an identifying number between N-1 and 1 also being responsive to the respectively numbered position determining pulse signal for selecting those of the pulses of the respective predetermined binary pulse signal which are substantially coincident with the pulses of the respectively numbered position determining pulse signal to derive the respectively numbered output pulse signal when the respectively numbered bit has the first level so that each of said output pulse signals which has an identifying number between N-1 and M+1 having G pulses which are contiguous but not coincident with the respective G pulses of all the preceding higher numbered output pulse signals and each of said output pulse signals which has an identifying number equal to or less than M having less than G pulses which are distributed among and contiguous with different ones of the G pulses of the output pulse signals which have identifying numbers between N and M+1; and OR gate means for additively combining the pulses of said output pulse signals to generate said pulse signal representing the magnitude of the analog signal.