Abstract Disclosed is a stepping motor control utilizing a microprocessor. The control is suitable for driving one or more stepping motors one at a time or in unison. In the illustrated embodiment when plural motors are driven together they are driven at the same rate or at rates in a fixed proportion to one another although several of the features of the invention are suitable for use in circuits providing contouring control; i.e., where separate motors are driven at separate stepping rates proportional to the relative distances each is to traverse for a single movement. An acceleration/deceleration circuit is utilized which provides simple yet highly accurate and efficient control of the stepping motors. Feed rate compensation for simultaneous drive of two motors is provided. Also a means is provided to allow stepping rates in excess of the counting rate capability of the microprocessor.
An electronic pulse counter for counting pulses up to an n digit number x of modulus m comprising: (a) a modulus m down counter having a capacity of q digits where m is an integer with a minimum value of one, said down counter being of the type which counts down through zero to q digits of (m-1) including; (i) means to input the q lowest order digits of x into the register(s) of said downcounter; (ii) means to input the pulses to be counted into said downcounter; (iii) means producing an output pulse from said downcounter each time it counts to zero; (b) a computer including means to count n-q digits from a pulsed source; (c) means to input the highest order n-q digits of X into the computer; (d) means to input the output pulses from the downcounter into the computer; (e) output means from said computer to indicate that the highest order n-q digits have been counted; and (f) means responsive to the coincidence of said last mentioned output means and an output pulse from said downcounter to indicate that the count is complete.
Claim 2
Dependent Claim
187 words
An electronic pulse counter for counting pulses up to an n digit number x of modulus m comprising: (a) a modulus m down counter having a capacity of q digits where m is an integer with a minimum value of one, said down counter being of the type which counts down through zero to q digits of (m-1) including; (i) means to input the q lowest order digits of x into the register(s) of said downcounter; (ii) means to input the pulses to be counted into said downcounter; (iii) means producing an output pulse from said downcounter each time it counts to zero; (b) a computer including means to count n-q digits from a pulsed source; (c) means to input the highest order n-q digits of X into the computer; (d) means to input the output pulses from the downcounter into the computer; (e) output means from said computer to indicate that the highest order n-q digits have been counted; and (f) means responsive to the coincidence of said last mentioned output means and an output pulse from said downcounter to indicate that the count is complete.
Claim 3
Dependent Claim
19 words
The pulse counter of claim 1 wherein said downcounter counts down by incrementing the complement of the number stored.