Motor speed control apparatus

Claim 1

A motor speed control apparatus comprising: a motor; a frequency generating means coupled to said motor to be controlled for generating a detective frequency output signal having a frequency proportional to the rotational speed of said motor; a clock pulse generating means for generating a stable clock pulse train; a rotational speed error detecting means for generating a rotational speed error pulse train output in response to the output signals of said frequency generating means and of said clock pulse generating means, the pulse width of said rotational speed error pulse train corresponding to the rotational speed error of said motor; a low pass filtering means, coupled to said rotational speed error detecting means, for changing said rotational speed error pulse train to a smooth voltage signal corresponding to the pulse width of said rotational speed error pulse train; a low frequency reinforcing means, coupled to said low pass filtering means and comprising an active filter whose response is -20 dB/decade at its low frequency region of operation and whose response is flat at its high frequency region of operation, for reinforcing the low frequency component included in said rotational speed error pulse train; and a motor driving means, coupled to said low frequency reinforcing means, for driving said motor, whereby said motor generates a torque corresponding to the output of said motor driving means; wherein said rotational speed error detecting means comprises: a detective digital pulse train generating means for generating a detective digital pulse train output in response to the output signal of said frequency generating means; a first fixed-width pulse train generating means having a divide-by-N counter (N being an integer), which starts counting the output pulses of said clock generating means when said divide-by-N counter is triggered by an edge of a predetermined polarity of said detective digital pulse train, and which generates a first fixed-width pulse train output, the pulse width of which is equal to the counting time of said divide-by-N counter; a second fixed-width pulse train generating means having a divide-by-M counter (M being an integer), which starts counting the output pulses of said clock generating means when said divide-by-M counter is triggered by an edge of a predetermined polarity of said first fixed-width pulse train, and which generates a second fixed-width pulse train output, the pulse width of which is equal to the counting time of said divide-by-M counter; and a pulse combining circuit means having two input terminals, to one of which the output of said first fixed-width pulse train generating means is coupled, and to the other of which the output of said second fixed-width pulse train generating means is coupled, said pulse combining means producing a rotational speed-error pulse train by combining said output signal from said first fixed-width pulse train generating means and said output signal from said second fixed-width pulse train generating means.