CVSD Multiple conference system

Claim 2

A CVSD multiple conference system comprising: a plurality of conferencers each having a plurality of accumulators each for outputting a CVSD conference, and including means in each conferencer for selectively placing any one or all or any combination of a plurality of linear format inputs representing the size or weight of CVSD signals in any one or all or any combination of the accumulators in its respective conferencer independently of the accumulators in the remaining conferencers, and means for deriving from at least a designated one of said accumulators an output so that when the designated accumulator is selected to contain a combination of a plurality of said inputs, said output represents a conference of said CVSD signals.

Claim 3

The invention according to claim 1 wherein each said conferencer comprises: arithmetic logic unit means for performing functions on said inputs and on the contents of said accumulators, including the functions of (a) summing an input with the contents of an accumulator and (b) leaving said contents unaltered; and memory means for storing the functions to be performed on each of said inputs by said arithmetic logic unit means for each of said accumulators.

Claim 4

The invention according to claim 2 wherein each of said CVSD signals is comprised of a CVSD bit and each said conferencer comprises: means responsive to said CVSD bits as sign bits for choosing said summing to be additive or subtractive.

Claim 5

The invention according to claim 3 wherein said last mentioned means comprises means transmitting said CVSD bits as sign bits to said arithmetic logic unit means for choosing addition or subtraction when said memory means chooses said summing function.

Claim 6

The invention according to claim 2 wherein each said conferencer further comprises scaler means for performing functions on said inputs before application of the inputs to said arithmetic logic unit means, including the functions of (a) scaling the magnitude of an input and, (b) leaving said magnitude unaltered, and wherein said memory means also stores the functions to be performed on each of said inputs by said scaler means for each of said accumulators.

Claim 7

The invention according to claim 2 wherein said inputs are cyclicly sampled in sequential time division multiplex order, thereby providing a repeated sampling cycle having plural multiplex time slots, and wherein: each conferencer includes means responsive to CVSD bits, each corresponding to one of said CVSD signals, as sign bits for choosing said summing to be additive or subtractive; said memory means comprises at least one storage location for each of said plurality of inputs and is clocked from location to location at rate R1 in synchronism with the multiplexed time slots of said inputs, each storage location having a multibit word containing M sub-words; each conferencer includes means connected to the output of its memory means for receiving said multibit words from said storage locations at rate R1, and multiplexing said M sub-words from said R1 rate to a faster rate R2; and each conferencer includes means for sequencing its set of accumulators at said rate R2 such that during each multiplex time slot of a CVSD signal each accumulator in a conferencer is accessed for a given sub-time slot, such that during the first sub-time slot of a given multiplex time slot an input is available to the first accumulator in each of said conferencers, and during the second sub-time slot of the same said given multiplex time slot the same said input is available to the second accumulator in each of said conferencers, and so on, each conferencer having at least M accumulators where M equals the ratio of R2 to R1, such that said M memory sub-words provide control codes for said arithmetic logic unit means for M conferenced accumulations in its conferencer during each multiplex time slot of a CVSD signal.

Claim 8

The invention according to claim 6 comprising a pair of buses each connected to all of said conferencers, one bus for carrying said inputs and the other bus for loading the memory means in said conferencers, and wherein each conferencer comprises: an address register for receiving from said other bus the address to be written into in said memory means; a data register for receiving from said other bus the data to be written into said address in said memory means; a comparator for comparing the address in said address register against the currently sequenced input time slot on said one bus for outputting a coincidence signal; and a selector having a first state leaving each storage location in said memory means unaltered during sequencing thereof, and having a second state responsive to said coincidence signal from said comparator for gating the data from said data register into the memory location addressed by said address register.

Claim 9

The invention according to claim 1 wherein each said conferencer comprises: scaler means for performing functions on said inputs including the functions of (a) scaling the magnitude of an input and (b) leaving said magnitude unaltered; arithmetic logic unit means for performing functions on the inputs from said scaler means and on the contents of said accumulators, including the functions of (a) summing an input with the contents of an accumulator and, (b) leaving said contents unaltered; memory means for storing the functions to be performed on each of said inputs by said scaler means and said arithmetic logic unit means for each of said accumulators; means responsive to CVSD bits, each corresponding to one of said CVSD signals, as sign bits for choosing said summing to be additive or subtractive; and overload prevention means for preventing overflow of said accumulators beyond their capacity.

Claim 10

The invention according to claim 8 comprising means transmitting said CVSD bits as sign bits to said arithmetic logic unit means for choosing addition or subtraction when said memory means chooses said summing function, and wherein said overload prevention means comprises means for feeding back to said arithmetic logic unit means one or more of the most significant digits of the contents of said accumulators in combination with said CVSD sign bit for preventing addition or subtraction beyond the capacity of said accumulators.

Claim 11

The invention according to claim 8 wherein said inputs are cyclicly sampled in sequential time division multiplexed order, thereby providing a repeated sampling cycle having plural multiplex time slots, and wherein each said conferencer further comprises: decay means incrementally reducing the contents of said accumulators during each sampling cycle to reduce the contents of an accumulator to a given value after a plurality of cycles with no conference activity therein.

Claim 12

The invention according to claim 10 wherein said decay means comprises: a shift register in a feedback loop from the outputs of said accumulators for transmitting a decremented fractional value of the contents thereof to said arithmetic logic unit means during one of the multiplex time slots during each sampling cycle for subtraction from said contents.

Claim 13

The CVSD multiple conference system comprising: means for generating a plurality of linear digital data signals from a respective plurality of CVSD inputs; data bus means connected to the output of said generating means for receiving said signals; conferencing means connected to said bus means and including a plurality of accumulators each for outputting a conference of a multiplicity of said CVSD inputs and including means for selectively placing any said signal in any one or all or any combination of said accumulators; and means connected to the outputs of said accumulators for delivering CVSD outputs.

Claim 14

The CVSD multiple conference system comprising: means for generating a plurality of linear digital data signals from a respective plurality of CVSD inputs; data bus means connected to the output of said generating means for receiving said signals; conferencing means connected to said bus means and including a plurality of accumulators each for outputting a conference of a multiplicity of said CVSD inputs and including means for selectively placing any said signal in any one or all or any combination of said accumulators; and means connected to the outputs of said accumulators for delivering CVSD outputs.

Claim 15

The invention according to claim 12 wherein said conferencing means comprises: arithmetic logic unit means for performing functions on said signals and on the contents of said accumulators, including the functions of (a) summing a signal with the contents of an accumulator and (b) leaving the latter unaltered; and memory means for storing the function to be performed on each of said signals by said arithmetic logic unit means for each of said accumulators.

Claim 16

The invention according to claim 13 wherein said conferencing means further comprises means responsive to input CVSD bits, each corresponding to one of said CVSD inputs, as sign bits for choosing said summing to be additive or subtractive.

Claim 17

The invention according to claim 13 wherein: said generating means also outputs CVSD input bits, each corresponding to one of said CVSD inputs, to said bus means; and said conferencing means receives said CVSD bits and includes means transmitting said CVSD bits as a sign bits to said arithmetic logic unit means for choosing addition or subtraction when said memory means chooses said summing function.

Claim 18

The invention according to claim 15 wherein: said generating means outputs a multiple bit digital signal code to said bus means for each CVSD input bit, said code having a first signal value portion containing a plurality of bits representing the size or weight of the CVSD bit, said code having a second portion containing the CVSD bit; and said conferencing means comprises first transmission means delivering said first signal value portion of said code to a first input to said arithmetic logic unit means to be summed with accumulator contents when designated by said memory means, and comprises second transmission means delivering said CVSD bit portion of said code as a second input to said arithmetic logic unit means for choosing additive or subtractive summing in the latter according to the sign polarity of said CVSD bit.

Claim 19

The invention according to claim 13 wherein: said generating means outputs said signals in sequential time division multiplexed order on said bus means at a rate R1; and said plurality of accumulators comprises register means having a capacity of at least M words, one conference per word, and is clocked from word to word at a rate R2 which is greater than R1, and wherein M equals the ratio of R2 to R1.

Claim 20

The invention according to claim 17 wherein: said memory means includes at least one storage location for each of said plurality of CVSD inputs and is clocked from location to location at rate R1 in synchronism with the appearance of the respective said signal on said bus means, each storage location having a multibit word containing M sub-words; and said conferencing means includes means connected to the output of said memory means for receiving said multibit words from said storage locations at rate R1, and multiplexing said M sub-words from said R1 rate to said R2 rate in synchronism with said R2 rate clocking of said register means, such that each said M memory sub-words provide control codes for said arithmetic logic unit means for M conferenced accumulations for each CVSD input.

Claim 21

The invention according to claim 13 wherein said conferencing means comprises a plurality of conferencers connected to said bus means, each conferencer having its own set of said accumulators, its own said arithmetic logic unit means and its own said memory means, each conferencer generating a plurality of conferenced outputs.

Claim 22

The invention according to claim 19 wherein: said generating means outputs said signals in sequential time division multiplexed order on said bus means at rate R1 such that each said signal is available on said bus means during a given time slot; and said conferencers are connected in parallel to said bus means and each conferencer sequences its own set of accumulators at a rate R2 faster than R1 such that during each said time slot each accumulator in a conferencer is accessed for a given sub-time slot, such that during the first sub-time slot of a given time slot of said bus means a signal is available to the first accumulator in each of said conferencers, and during the second sub-time slot of the same said given time slot of said bus means the same said linear signal is available to the second accumulator in each of said conferencers and so on, each conferencer having at least as many accumulators as the number of sub-time slots in one time slot of said bus means.

Claim 23

The invention according to claim 20 wherein: said generating means outputs a multiple bit digital signal code to said bus means for each of CVSD input bits corresponding to said CVSD inputs, said code having a first numerical value portion containing a plurality of bits representing the size or weight of the CVSD bit, said code having a second portion containing the CVSD bit; each said conferencer comprises first transmission means delivering said first numerical value portion of said code to a first input to its arithmetic logic unit means to be summed with accumulator contents when designated by its memory means, and comprises second transmission means delivering said CVSD bit portion of said code as a sign bit to a second input to its arithmetic logic unit means for choosing additive or subtractive summing in the latter according to the sign polarity of the CVSD bit; the memory means of each conferencer includes at least one storage location for each of said plurality of CVSD inputs and is clocked from location to location at rate R1 in synchronism with the appearance of the respective said multiple bit signal on said bus means, each storage location having a multibit word containing M sub-words; and each conferencer includes means connected to the output of its memory means for receiving said multibit words from said storage locations at rate R1, and multiplexing said M sub-words from said R1 rate to said R2 rate in synchronism with said R2 rate clocking of its accumulators, such that said M memory sub-words provide control codes for said arithmetic logic unit means for M conferenced accumulations by each conferencer during each said CVSD input.

Claim 24

A CVSD multiple conference system comprising: a plurality of parallel conferencers; a data bus connected to all of said conferencers for making available to said conferencers a plurality of sequential time division multiplexed input signals, each signal comprising a multilevel digital linear code representing the size or weight of an input CVSD bit; each conferencer comprising: a plurality of accumulators for outputting a conference of a multiplicity of CVSD signals, each corresponding to one of said input CVSD bits; means sequentially accessing each of the accumulators in that conferencer in time division multiplex order for a sub-time slot of each input signal time slot on said bus, and for each sub-time slot either leaving the contents of the sequenced accumulator unaltered or additively or subtractively summing said multilevel digital linear code with said contents according to the polarity of said CVSD bit; and a memory having a plurality of storage locations providing control codes for each summation in each accumulator in its conferencer during each of said input signal time slots.

Claim 25

A CVSD multiple conference system comprising: a plurality of parallel conferencers; a data bus connected to all of said conferencers for making available to said conferencers a plurality of sequential time division multiplexed input signals, each signal comprising a multilevel digital linear code representing the size or weight of an input CVSD bit; each conferencer comprising: a plurality of accumulators for outputting a conference of a multiplicity of CVSD signals, each corresponding to one of said input CVSD bits; means sequentially accessing each of the accumulators in that conferencer in time division multiplex order for a sub-time slot of each input signal time slot on said bus, and for each sub-time slot either leaving the contents of the sequenced accumulator unaltered or additively or subtractively summing said multilevel digital linear code with said contents according to the polarity of said CVSD bit; and a memory having a plurality of storage locations providing control codes for each summation in each accumulator in its conferencer during each of said input signal time slots.

Claim 26

The invention according to claim 22 wherein each conferencer further comprises a scaler for altering the magnitude of said multilevel digital linear code from said bus in response to the control code from said memory for the current time slot of said bus and sub-time slot therein for the currently sequenced accumulator, for altering the volume level of the respective conferee's voice signal output from said accumulator.