US4163871A
Expired / Lapsed
US
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Digital CVSD telephone conference circuit
Assignee: International Telephone and Telegraph Corp
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Filing: 1977-12-22
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Granted: 1979-08-07
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Expires: 1997-12-22
Abstract
Abstract A six-telephone channel conference system features an all-digital CVSD (continuously variable slope delta modulation) conference bridge-like circuit. The delta modulation pulse train in each channel is transformed into a series of slope numbers which are processed by the conference circuit addition function to provide zero insertion loss, then by the subtraction function to provide 100% cancellation of a talker's voice to his ear. Transformation involves a sequential three-bit algorithm.
Inventors
- 👤 Charles R. Maggi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 23:18
CPC Classifications
H; H04; H04M; H04M3/00; H04M3/42; H04M3/56; H04M3/561
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
218 words
An all digital delta modulation telephone conference circuit comprising: first digital means to separately store in succession a plurality of sequential bits in each of a plurality of input delta modulation bit streams each originating from a different one of a plurality of phones, each of said plurality of bits being capable of having a plurality of different bit combinations, each of said plurality of different bit combinations being assigned a predetermined slope number, wherein said slope number indicates slope information of an analog signal represented by each of said plurality of streams; and second digital means coupled to said first means for sequentially receiving each of said plurality of bits, for adding from each bit stream correspondingly-occurring first binary bit combinations determined by said slope number assigned to each of said received plurality of bits to produce a sum digital signal including information from each of said phones, and for subtracting second binary bit combinations determined by said slope number assigned to each of said received plurality of bits from said sum digital signal to produce a plurality of output conference delta modulation bit streams each for a different one of said plurality of phones and each including information from all of said plurality of phones minus information from the associated one of said plurality of phones.
Claim 2
Dependent Claim
218 words
An all digital delta modulation telephone conference circuit comprising: first digital means to separately store in succession a plurality of sequential bits in each of a plurality of input delta modulation bit streams each originating from a different one of a plurality of phones, each of said plurality of bits being capable of having a plurality of different bit combinations, each of said plurality of different bit combinations being assigned a predetermined slope number, wherein said slope number indicates slope information of an analog signal represented by each of said plurality of streams; and second digital means coupled to said first means for sequentially receiving each of said plurality of bits, for adding from each bit stream correspondingly-occurring first binary bit combinations determined by said slope number assigned to each of said received plurality of bits to produce a sum digital signal including information from each of said phones, and for subtracting second binary bit combinations determined by said slope number assigned to each of said received plurality of bits from said sum digital signal to produce a plurality of output conference delta modulation bit streams each for a different one of said plurality of phones and each including information from all of said plurality of phones minus information from the associated one of said plurality of phones.
Claim 3
Dependent Claim
19 words
A circuit according to claim 1, wherein said second means first performs said adding and then performs said subtracting.
Claim 4
Dependent Claim
54 words
A circuit according to claim 2, wherein said first means includes a given number of a plurality of cascade connected input storage circuits, said given number being equal in number to said plurality of phones and each of said plurality of storage circuits is coupled to a different one of said plurality of phones.
Claim 5
Dependent Claim
19 words
A circuit according to claim 3, wherein each of said plurality of input storage devices is a flip flop.
Claim 6
Dependent Claim
17 words
A circuit according to claim 4, wherein each of said flip flops is a D-type flip flop.
Claim 7
Dependent Claim
12 words
A circuit according to claim 5, wherein said given number is six.
Claim 8
Dependent Claim
13 words
A circuit according to claim 2, wherein said plurality of phones number six.
Claim 9
Dependent Claim
67 words
A circuit according to claim 6, wherein said second means includes a programmable read only memory adder programmed with said first binary bit combinations to enable addition of said first binary bit combinations determined by said slope number, and a latch circuit coupled to a predetermined number of outputs of said adder and a predetermined number of address inputs to store a running sum of said addition.
Claim 10
Dependent Claim
43 words
A circuit according to claim 8, wherein said second means further includes a programmable read only memory subtractor programmed with said second binary bit combinations to enable subtraction of said second binary bit combinations from the total sum stored in said latch circuit.
Claim 11
Dependent Claim
17 words
A circuit according to claim 9, wherein said latch circuit includes a predetermined number of flip flops.
Claim 12
Dependent Claim
17 words
A circuit according to claim 10, wherein each of said flip flops is a D-type flip flop.
Claim 13
Dependent Claim
32 words
A circuit according to claim 11, wherein said predetermined number of outputs are the five least significant outputs, and said predetermined number of address inputs are the five least significant address inputs.
Claim 14
Dependent Claim
22 words
A circuit according to claim 12, wherein said latch circuit is coupled to the five least significant address inputs of said subtractor.
Claim 15
Dependent Claim
77 words
A circuit according to claim 13, wherein said second means further includes a tri-state buffer coupled to each of said plurality of input storage devices and a given number of address inputs of said adder and said subtractor, and a first source of timing signals to sequentially enable groups of said buffers to couple each of said plurality of bits in sequence to said given number of address inputs when said second means is adding and subtracting.
Claim 16
Dependent Claim
20 words
A circuit according to claim 14, wherein said given number of address inputs are the three most significant address inputs.
Claim 17
Dependent Claim
58 words
A circuit according to claim 15, wherein said second means further includes an intermediate sequential storage circuit coupled to the two most significant outputs of said subtractor to store sequentially in said intermediate storage circuit the result of subtraction in said subtractor, and a second source of timing signals to sequentially control said intermediate storage circuit when adding.
Claim 18
Dependent Claim
25 words
A circuit according to claim 16, wherein said intermediate storage circuit includes a plurality of flip flops equal in number to said plurality of phones.
Claim 19
Dependent Claim
17 words
A circuit according to claim 17, wherein each of said flip flops is a JK-type flip flop.
Claim 20
Dependent Claim
23 words
A circuit according to claim 18, wherein each of said first and second source of timing signals include a four-stage Johnson octal counter.
Claim 21
Dependent Claim
63 words
A circuit according to claim 19, wherein said second means further includes a plurality of output storage circuits equal in number to said plurality of phones, each of said output storage circuits being coupled to a different of said flip flops of said intermediate storage circuit, each of said output storage circuit providing a different one of said plurality of conference bit streams.
Claim 22
Dependent Claim
19 words
A circuit according to claim 20, wherein each of said plurality of output storage circuits include a flip flop.
Claim 23
Dependent Claim
17 words
A circuit according to claim 21, wherein each of said flip flops is a D-type flip flop.
Claim 24
Dependent Claim
67 words
A circuit according to claim 2, wherein said second means includes a programmable read only memory adder programmed with said first binary bit combinations to enable addition of said first binary bit combinations determined by said slope number, and a latch circuit coupled to a predetermined number of outputs of said adder and a predetermined number of address inputs to store a running sum of said addition.
Claim 25
Dependent Claim
43 words
A circuit according to claim 23, wherein said second means further includes a programmable read only memory subtractor programmed with said second binary bit combinations to enable subtraction of said second binary bit combinations from the total sum stored in said latch circuit.
Claim 26
Dependent Claim
17 words
A circuit according to claim 24, wherein said latch circuit includes a predetermined number of flip flops.
Claim 27
Dependent Claim
17 words
A circuit according to claim 25, wherein each of said flip flops is a D-type flip flop.
Claim 28
Dependent Claim
32 words
A circuit according to claim 26, wherein said predetermined number of outputs are the five least significant outputs, and said predetermined number of address inputs are the five least significant address inputs.
Claim 29
Dependent Claim
22 words
A circuit according to claim 27, wherein said latch circuit is coupled to the five least significant address inputs of said subtractor.
Claim 30
Dependent Claim
72 words
A circuit according to claim 28, wherein said second means further includes a tri-state buffer coupled to said first means and a given number of address inputs of said adder and said subtractor, and a first source of timing signals to sequentially enable groups of said buffers to couple each of said plurality of bits in sequence to said given number of address inputs when said second means is adding and subtracting.
Claim 31
Dependent Claim
20 words
A circuit according to claim 29, wherein said given number of address inputs are the three most significant address inputs.
Claim 32
Dependent Claim
58 words
A circuit according to claim 30, wherein said second means further includes an intermediate sequential storage circuit coupled to the two most significant outputs of said subtractor to store sequentially in said intermediate storage circuit the result of subtraction in said subtractor, and a second source of timing signals to sequentially control said intermediate storage circuit when adding.
Claim 33
Dependent Claim
25 words
A circuit according to claim 31, wherein said intermediate storage circuit includes a plurality of flip flops equal in number to said plurality of phones.
Claim 34
Dependent Claim
17 words
A circuit according to claim 32, wherein each of said flip flops is a JK-type flip flop.
Claim 35
Dependent Claim
23 words
A circuit according to claim 33, wherein each of said first and second source of timing signals include a four-stage Johnson octal counter.
Claim 36
Dependent Claim
63 words
A circuit according to claim 34, wherein said second means further includes a plurality of output storage circuits equal in number to said plurality of phones, each of said output storage circuits being coupled to a different of said flip flops of said intermediate storage circuit, each of said output storage circuit providing a different one of said plurality of conference bit streams.
Claim 37
Dependent Claim
19 words
A circuit according to claim 35, wherein each of said plurality of output storage circuits include a flip flop.
Claim 38
Dependent Claim
17 words
A circuit according to claim 36, wherein each of said flip flops is a D-type flip flop.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-08-06 | 1983-02-05 | 1983-08-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-08-06 | 1987-02-05 | 1987-08-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-08-06 | 1991-02-05 | 1991-08-07 | $7700.00 | Window Closed / Lapsed |