Patent US4358690A successfully refreshed from Google Patents.
US4358690A
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Digital voltage comparator
Assignee: AT&T Teletype Corp
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Filing: 1980-07-18
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Granted: 1982-11-09
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Expires: 2000-07-18
Abstract
Abstract A digital voltage comparator is illustrated including a cross-coupled latch 10 having input nodes 12 and 14. After the input nodes 12 and 14 of the latch 10 have been respectively preloaded to the input A and reference E voltage levels during the active state of clock phase φ 1 , the latch is allowed to arrive at a stable state during the active state of clock phase φ 2 . Thereafter, when clock phase φ 3 is active, the output of the latch 10 is coupled to the input of a single stage shift register 20. The output of the shift register 20 is fed to inverters 22 and 26 and through a voltage divider for preloading the node 14 of the latch 10 during the next active state of clock phase φ 1 .
Inventors
- 👤 Gary B. Ollendick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 04:58
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356052; H03K3/35606
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
302 words
A digital voltage comparator for comparing an input signal (A) with a reference voltage (E) comprising: a bistable latch (10) having first and second nodes (12, 14), first means (36) for preloading said first node (12) to a voltage level determined by the input signal (A), second means (70) for preloading said second node (14) to voltage level (C) determined by the reference voltage (E), third means (46) for subsequently allowing the latch (10) to race to a stable state as determined by the voltage levels (B, C) of said nodes (12, 14), fourth means (20) for storing a signal level (D) related to the stable state of said latch (10), fifth means (26) responsive to the signal level (D) of said fourth means (20) for providing said reference voltage (E) to said second means (70) during preloading of said latch (10) subsequent to the storing of the signal level (D) related to the stable state of said latch (10) by said fourth means (20), sixth means (22) for providing an output signal (F) which is related to a stable state of said latch (10), said sixth means (22) provides an output signal (F) from the storage means (20) which is related to the input signal (A) to the latch (10) during a preceding time period, a system clock (18) having a plurality of clock phases (φ 1 , φ 2 , φ 3 ), said first and second means (36, 70), being controlled by a first clock phase (φ 1 ) of said system clock (18), said third means (46) being controlled by a second clock phase (φ 2 ) of said system clock (18), and said fourth means (20) being controlled by said first and a third clock phase (φ 1 , φ 3 ) of said system clock (18).
Claim 2
Dependent Claim
302 words
A digital voltage comparator for comparing an input signal (A) with a reference voltage (E) comprising: a bistable latch (10) having first and second nodes (12, 14), first means (36) for preloading said first node (12) to a voltage level determined by the input signal (A), second means (70) for preloading said second node (14) to voltage level (C) determined by the reference voltage (E), third means (46) for subsequently allowing the latch (10) to race to a stable state as determined by the voltage levels (B, C) of said nodes (12, 14), fourth means (20) for storing a signal level (D) related to the stable state of said latch (10), fifth means (26) responsive to the signal level (D) of said fourth means (20) for providing said reference voltage (E) to said second means (70) during preloading of said latch (10) subsequent to the storing of the signal level (D) related to the stable state of said latch (10) by said fourth means (20), sixth means (22) for providing an output signal (F) which is related to a stable state of said latch (10), said sixth means (22) provides an output signal (F) from the storage means (20) which is related to the input signal (A) to the latch (10) during a preceding time period, a system clock (18) having a plurality of clock phases (φ 1 , φ 2 , φ 3 ), said first and second means (36, 70), being controlled by a first clock phase (φ 1 ) of said system clock (18), said third means (46) being controlled by a second clock phase (φ 2 ) of said system clock (18), and said fourth means (20) being controlled by said first and a third clock phase (φ 1 , φ 3 ) of said system clock (18).
Claim 3
Dependent Claim
76 words
The digital voltage comparator of claim 1 wherein: said first and third clock phases (φ 1 , φ 3 ), are non-overlapping, and said first and second means (36, 70), includes first and second transistors (36, 70) connected as clocked pass devices which are both controlled by said first clock phase (φ 1 ) and serve to couple said input signal (A) and said reference voltage (E) to the nodes (12, 14) of said latch (10).
Claim 4
Dependent Claim
51 words
The digital voltage comparator of claim 2 wherein: said fourth means (20) is in the form of a one stage shift register, the input to which is controlled by said third clock phase (φ 3 ) and the output of which is controlled by said first clock phase (φ 1 ).
Claim 5
Dependent Claim
28 words
The digital voltage comparator of claim 3 wherein: the level (D) of said shift register (20) provides the reference voltage (E) to said second clocked pass transistor (70).
Claim 6
Dependent Claim
72 words
The digital voltage comparator of claim 4 wherein: the active state of said first clock phase (φ 1 ) is non-overlapping with the active states of said second and third clock phases (φ 2 , φ 3 ), and the beginning of the active state of said third clock phase (φ 3 ) is delayed with respect to the beginning of the active state of said second clock phase (φ 2 ).
Claim 7
Dependent Claim
272 words
A digital voltage comparator for comparing an input signal (A) with a reference voltage (E) comprising: a bistable latch (10) having first and second nodes (12, 14), first means (36) for preloading said first node (12) to a voltage level determined by the input signal (A), second means (70) for preloading said second node (14) to voltage level (C) determined by the reference voltage (E), third means (46) for subsequently allowing the latch (10) to race to a stable state as determined by the preloaded voltage levels (B, C) of said nodes (12, 14), fourth means (20) for storing a signal level (D) related to the stable state of said latch (10), fifth means (26) responsive to the signal level (D) of said fourth means (20) for providing said reference voltage (E) to said second means (70) during preloading of said latch (10) subsequent to the storing of the signal level (D) related to the stable state of said latch (10) by said fourth means (20), sixth means (22) for providing an output signal (F) which is related to a stable state of said latch (10), a system clock (18) having a plurality of clock phases (φ 1 , φ 2 and φ 3 ), said first and second means (36, 70), being controlled by a first clock phase (φ 1 ) of said system clock (37), said third means (46) being controlled by a second clock phase (φ 2 ) of said system clock (18), and said fourth means (20) being controlled by said first (φ 1 ) and said third (φ 3 ) clock phases of said system clock (18).
Claim 8
Dependent Claim
272 words
A digital voltage comparator for comparing an input signal (A) with a reference voltage (E) comprising: a bistable latch (10) having first and second nodes (12, 14), first means (36) for preloading said first node (12) to a voltage level determined by the input signal (A), second means (70) for preloading said second node (14) to voltage level (C) determined by the reference voltage (E), third means (46) for subsequently allowing the latch (10) to race to a stable state as determined by the preloaded voltage levels (B, C) of said nodes (12, 14), fourth means (20) for storing a signal level (D) related to the stable state of said latch (10), fifth means (26) responsive to the signal level (D) of said fourth means (20) for providing said reference voltage (E) to said second means (70) during preloading of said latch (10) subsequent to the storing of the signal level (D) related to the stable state of said latch (10) by said fourth means (20), sixth means (22) for providing an output signal (F) which is related to a stable state of said latch (10), a system clock (18) having a plurality of clock phases (φ 1 , φ 2 and φ 3 ), said first and second means (36, 70), being controlled by a first clock phase (φ 1 ) of said system clock (37), said third means (46) being controlled by a second clock phase (φ 2 ) of said system clock (18), and said fourth means (20) being controlled by said first (φ 1 ) and said third (φ 3 ) clock phases of said system clock (18).
Claim 9
Dependent Claim
123 words
The digital voltage comparator of claim 6 wherein: said first and third clock phases (φ 1 , φ 3 ) are non-overlapping, and said first and second means (36, 70) include first and second transistors (36, 70) connected as clocked pass devices which are both controlled by said first clock phase (φ 1 ) and serve to couple said input signal (A) and said reference voltage (E) to the nodes (12, 14) of said latch (10), and said fourth means (20) is in the form of a one bit shift register, the input to said shift register (20) is controlled by said third clock phase (φ 3 ) and the output of which is controlled by said first clock phase (φ 1 ).
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-11-08 | 1986-05-10 | 1986-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-11-08 | 1990-05-10 | 1990-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-11-08 | 1994-05-10 | 1994-11-09 | $7700.00 | Window Closed / Lapsed |