Patent US4358340A successfully refreshed from Google Patents.
US4358340A
Expired / Lapsed
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Submicron patterning without using submicron lithographic technique
Assignee: Texas Instruments Inc
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Filing: 1980-07-14
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Granted: 1982-11-09
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Expires: 2000-07-14
Abstract
Abstract A method for the fabrication of submicron devices, without the use of submicron lithography. Vertical "zero undercut" etching techniques are employed, in order to convert the submicron thickness of a deposited thin film conductor layer and a thin film insulation layer into submicron gate widths that can be used in a wide variety of devices, including MOS field effect devices, for example. The conversion is achieved by depositing a thin film conductor layer of submicron thickness across a vertical step between adjacent insulator surfaces, and then vertically etching until the only remaining portion of the conductor layer is that portion adjacent the vertical step. The remaining insulation not covered by conductor is then removed. Thus, an insulated gate is provided having a submicron width approximately equal to the thickness of the conductor layer as initially deposited.
Inventors
- 👤 Horng-Sen Fu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 05:03
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0221; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D64/0133; H10P; H10P76/00; H10P76/40; H10P76/408; H10P76/4085; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/947
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
136 words
A method for the fabrication of an insulated gate semiconductor device comprising the steps of: (a) forming an adherent insulation layer on a semiconductor substrate; (b) selectively thinning a portion of said insulation layer to provide a substantially vertical step at the location where the resulting thin portion adjoins the original thick portion; (c) depositing a conductor film of micron or submicron thickness, on and near said vertical steps; (d) thinning at least a portion of said conductor film until the only portion thereof remaining in the vicinity of said step is a narrow section directly adjacent said step, on the thin portion of said insulation layer; (e) using the remaining conductor as a mask, selectively removing the insulation not covered by the conductor, whereby an insulated gate is formed; (f) and then completing said device.
Claim 2
Independent Claim
136 words
A method for the fabrication of an insulated gate semiconductor device comprising the steps of: (a) forming an adherent insulation layer on a semiconductor substrate; (b) selectively thinning a portion of said insulation layer to provide a substantially vertical step at the location where the resulting thin portion adjoins the original thick portion; (c) depositing a conductor film of micron or submicron thickness, on and near said vertical steps; (d) thinning at least a portion of said conductor film until the only portion thereof remaining in the vicinity of said step is a narrow section directly adjacent said step, on the thin portion of said insulation layer; (e) using the remaining conductor as a mask, selectively removing the insulation not covered by the conductor, whereby an insulated gate is formed; (f) and then completing said device.
Claim 3
Dependent Claim
34 words
A method as in claim 1 wherein said vertical step is provided by selectively etching to remove the thinned portion, followed by regrowing or depositing a thin layer to partially replace the removed portion.
Claim 4
Dependent Claim
18 words
A method as in claim 1 wherein said semiconductor is silicon and said insulation layer is silicon oxide.
Claim 5
Dependent Claim
13 words
A method as in claim 1 wherein said conductor comprises doped polycrystalline silicon.
Claim 6
Dependent Claim
33 words
A method as in claim 1 wherein said device comprises an MOS field effect device, said semiconductor comprises monocrystalline silicon, said insulation layer comprises silicon oxide, and said conductor comprises doped polycrystalline silicon.
Claim 7
Dependent Claim
15 words
A method as in claim 1 wherein the gate width is less than one micron.
Claim 8
Dependent Claim
15 words
A method as in claim 5 wherein the gate width is less than one micron.
Claim 9
Independent Claim
137 words
A method of fabricating an insulted conductor gate on a semiconductor substrate comprising: (a) selectively etching an insulating layer on a surface of a semiconductor substrate so as to form two thickness levels of the insulating layer and a vertical edge therebetween; (b) forming a conductive layer covering the vertical edge and adjacent insulating layer; (c) vertically etching said conductor so as to expose the insulating layer lying thereunder except that conductor adjacent the vertical edge, whereby a region of conductor results overlying a portion of the insulating layer, the region of said conductor having a length approximately equal to the initial thickness of the conductive layer; (d) then vertically etching the insulator not covered by the conductor, until all such insulator is removed, leaving only an insulated conductor gate for use in fabricating a semiconductor device.
Claim 10
Independent Claim
137 words
A method of fabricating an insulted conductor gate on a semiconductor substrate comprising: (a) selectively etching an insulating layer on a surface of a semiconductor substrate so as to form two thickness levels of the insulating layer and a vertical edge therebetween; (b) forming a conductive layer covering the vertical edge and adjacent insulating layer; (c) vertically etching said conductor so as to expose the insulating layer lying thereunder except that conductor adjacent the vertical edge, whereby a region of conductor results overlying a portion of the insulating layer, the region of said conductor having a length approximately equal to the initial thickness of the conductive layer; (d) then vertically etching the insulator not covered by the conductor, until all such insulator is removed, leaving only an insulated conductor gate for use in fabricating a semiconductor device.
Claim 11
Dependent Claim
23 words
A method of fabricating insulative gates on a semiconductor substrate as recited in claim 7 wherein the insulating layer consists of silicon dioxide.
Claim 12
Dependent Claim
29 words
A method of fabricating insulative gates on a semiconductor substrate as recited in claim 8 wherein the conductive layer is selected from polysilicon, aluminum, refractive metals, and metal silicides.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-11-08 | 1986-05-10 | 1986-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-11-08 | 1990-05-10 | 1990-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-11-08 | 1994-05-10 | 1994-11-09 | $7700.00 | Window Closed / Lapsed |