Patent US4356566A successfully refreshed from Google Patents.
US4356566A
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Synchronizing signal detecting apparatus
Assignee: Panasonic Holdings Corp
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Filing: 1980-02-04
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Granted: 1982-10-26
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Expires: 2000-02-04
Abstract
Abstract A synchronizing signal detecting circuit for synchronizing digital data receiving equipment is disclosed. Digital signals consisting of data and synchronizing signals obtained by repeating a predetermined pulse pattern many times are fed to a shift register in succession in synchronism with clock pulses. A gate circuit connected to the shift register detects the synchronization pulse pattern. A detector circuit detects a duration period of a coincidence signal which is the output of the gate circuit, and outputs a synchronous detection signal when the duration period of the coincidence signal exceeds the predetermined value. This synchronizing signal detecting circuit can detect synchronizing signals even when data errors are produced to some extent.
Inventors
- 👤 Ryoichi Wada
- 👤 Takanori Seno
- 👤 Mitsuharu Tsuchiya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:59
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/04; H04L7/041; H04L7/042; G; G11; G11B; G11B20/00; G11B20/10; G11B20/12; H04L7/08; H04N; H04N5/00; H04N5/76; H04N5/91; H04N5/93; H04N5/932
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
98 words
A synchronizing signal detecting circuit comprising a shift register which introduces input pulses in succession in synchronism with clock pulses, a gate circuit which detects whether the contents of said shift register corresponds to a fixed predetermined pulse pattern and which procudes a coincidence signal when the contents of said shift register corresponds to said fixed predetermined pulse pattern, and a detector circuit which is connected to said gate circuit and which detects a duration period of said coincidence signal, said duration period corresponding to the period of a fixed predetermined number of said fixed predetermined pulse patterns.
Claim 2
Dependent Claim
98 words
A synchronizing signal detecting circuit comprising a shift register which introduces input pulses in succession in synchronism with clock pulses, a gate circuit which detects whether the contents of said shift register corresponds to a fixed predetermined pulse pattern and which procudes a coincidence signal when the contents of said shift register corresponds to said fixed predetermined pulse pattern, and a detector circuit which is connected to said gate circuit and which detects a duration period of said coincidence signal, said duration period corresponding to the period of a fixed predetermined number of said fixed predetermined pulse patterns.
Claim 3
Dependent Claim
37 words
A synchronizing signal detecting circuit according to claim 1, wherein said detector circuit comprises an up-down counter which operates by being switched to either one of a count-up or a count-down operation depending upon said coincidence signal.
Claim 4
Dependent Claim
50 words
A synchronizing signal detecting circuit according to claim 1, wherein said detector circuit consists of a circuit which electrically charges a capacitor according to a time constant determined by said coincidence signal, and a comparator circuit which compares a voltage across the terminals of said capacitor with a predetermined voltage.
Claim 5
Dependent Claim
66 words
A synchronizing signal detecting circuit according to claim 1, 2 or 3, wherein said gate circuit brings the length of the shift register into conformity with the length of a pulse pattern when the synchronous signals are composed of a plurality of predetermined pulse patterns, and wherein said gate circuit further detects the identity of patterns even when said pulse patterns circulate in said shift register.
Claim 6
Dependent Claim
88 words
A synchronizing signal detecting circuit according to claim 1, wherein said predetermined pulse pattern is "1100", and when the synchronizing signals consists of: a plurality of repetitions of said pulse pattern, and when an ANDed output of (1) an inverted signal of an exclusive OR output of a first bit and a third bit from the input side of said shift register and of (2) an input signal and a fourth bit becomes a predetermined logic level, said predetermined pulse pattern is produced as a coincidence detection signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-10-25 | 1986-04-26 | 1986-10-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-10-25 | 1990-04-26 | 1990-10-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-10-25 | 1994-04-26 | 1994-10-26 | $7700.00 | Window Closed / Lapsed |