MOS Integrated circuit structure for discretionary interconnection

Claim 2

At least two MOS transistors on a common substrate of a first conductivity type, each transistor comprising source and drain regions of a second conductivity type opposite said first conductivity type and a gate; at least one of said source and drain regions being common to each of said two transistors; means for contacting each of said source and drain regions at two locations so that said regions can act as both source or drain regions and as interconnection underpasses; and metallized connection means for supplying current to said MOS transistors, said connection means passing over each of said source and drain regions and over said gate, and said connection means lying between said contact means for each of said source and said drain regions.

Claim 3

A CMOS integrated circuit comprising pairs of complementary N-channel and P-channel devices, each transistor comprising source and drain regions and a gate; and contact means for contacting each of said source and drain regions at two locations so that said regions can act as both source or drain regions and as interconnection underpasses; and metallized connection means for supplying current to said MOS transistors, said connection means passing over each of said source and drain regions and over said gate, and said connection means lying between said contact means for each of said source and said drain regions.

Claim 4

A CMOS integrated circuit comprising pairs of complementary N-channel and P-channel devices, each transistor comprising source and drain regions and a gate; and contact means for contacting each of said source and drain regions at two locations so that said regions can act as both source or drain regions and as interconnection underpasses; and metallized connection means for supplying current to said MOS transistors, said connection means passing over each of said source and drain regions and over said gate, and said connection means lying between said contact means for each of said source and said drain regions.

Claim 5

The CMOS integrated circuit of claim 2, where said contact means are approximately equally spaced for each of said source and drain regions, the source and drain regions of the P-channel devices abutting their gates in an amount greater than the source and drain abutment to the gates of the N-channel devices.

Claim 6

An MOS integrated circuit comprising a substrate region of first conductivity type, a plurality of unit cells each comprising a cluster of MOS transistors at least two of which have common source and drain regions of opposite conductivity type to said substrate region, and each transistor having a gate and metallic connection means for supplying current to said MOS transistors, said connection means passing over each of said source and drain regions and over said gates, the improvement comprising alignment of the source gate and drain regions substantially parallel with a first direction in the plane of said circuit and alignment of said connection means substantially parallel with second direction perpendicular to said first direction in the plane of said circuit.

Claim 7

An MOS integrated circuit comprising a substrate region of first conductivity type, a plurality of unit cells each comprising a cluster of MOS transistors at least two of which have common source and drain regions of opposite conductivity type to said substrate region, and each transistor having a gate and metallic connection means for supplying current to said MOS transistors, said connection means passing over each of said source and drain regions and over said gates, the improvement comprising alignment of the source gate and drain regions substantially parallel with a first direction in the plane of said circuit and alignment of said connection means substantially parallel with second direction perpendicular to said first direction in the plane of said circuit.

Claim 8

A CMOS integrated circuit comprising of unit cells each comprising a cluster of pairs of complementary transistors each of which has source and drain regions and a gate, and further including a pair of contact means for each of said source and drain regions so that said regions can act as both source or drain regions and as interconnection underpasses, said source and drain regions, said gates, and said pairs of contact means all laying substantially parallel with each other.

Claim 9

A CMOS integrated circuit comprising of unit cells each comprising a cluster of pairs of complementary transistors each of which has source and drain regions and a gate, and further including a pair of contact means for each of said source and drain regions so that said regions can act as both source or drain regions and as interconnection underpasses, said source and drain regions, said gates, and said pairs of contact means all laying substantially parallel with each other.

Claim 10

The CMOS integrated circuit of claim 5, further including a pair of metallic conduction means for supplying current to said complementary pairs in each cluster, said connection means passing over said source and drain regions between said pairs of contact regions and over said gates, and said connection means being perpendicular to said source and drain regions, said gates, and said pairs of contact means.

Claim 11

The CMOS circuit of claim 6, where each of said unit cells consists of a cluster of three pairs of complementary devices.

Claim 12

The CMOS circuit of claim 6, further including a pair of enhanced conductivity regions in each unit cell for making contact to said pair of metallic connection means.

Claim 13

The CMOS integrated circuit of claim 6, further including at least two unit cells having separate P conductivity-type wells for the location of the N-channel transistors in each cluster.

Claim 14

The CMOS integrated circuit of claim 7, where the source and drain regions of the P-channel transistors abut their respective gates along substantially all of their total peripheral widths and the source and drain regions of the N-channel transistors abut their respective gates along substantially less than their total peripheral widths in order to achieve an approximate match between the electrical characteristics of N- and P-channel transistors.