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US4356502A
Expired / Lapsed
US
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Protection circuit for a semiconductor device
Assignee: Toshiba Corp
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Filing: 1979-12-14
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Granted: 1982-10-26
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Expires: 1999-12-14
Abstract
Abstract A protection circuit for a semiconductor substrate comprises a semiconductor substrate of a first conductivity type, a first region of a second conductivity type formed in the semiconductor substrate, a second region of the first conductivity type formed in the first region, a means for applying a reverse bias to a PN junction formed between the semiconductor substrate and the first region and a PN junction formed to the first and second regions, and a wiring for electrically connecting the second region to the semiconductor device to be protected.
Inventors
- 👤 Tetsuo Yamada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:00
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/611
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
105 words
A protection circuit for a semiconductor device formed in a common semiconductor chip with said circuit comprising: a semiconductor substrate of a first conductivity type; a first region of a second conductivity type formed in said semiconductor substrate; a second region of said first conductivity type formed in said first region; means for applying a constant potential to said first region to reverse bias a PN junction formed between said semiconductor substrate and said first region and to reverse bias a PN junction formed between said first and second regions; and means for electrically connecting said second region and said semiconductor device to be protected.
Claim 2
Dependent Claim
105 words
A protection circuit for a semiconductor device formed in a common semiconductor chip with said circuit comprising: a semiconductor substrate of a first conductivity type; a first region of a second conductivity type formed in said semiconductor substrate; a second region of said first conductivity type formed in said first region; means for applying a constant potential to said first region to reverse bias a PN junction formed between said semiconductor substrate and said first region and to reverse bias a PN junction formed between said first and second regions; and means for electrically connecting said second region and said semiconductor device to be protected.
Claim 3
Dependent Claim
41 words
A protection circuit according to claim 1, further including: insulating means covering said substrate and said first and second regions; and an auxiliary electrode in said insulating means, partially overlying the surface of the first region of the second conductivity type.
Claim 4
Dependent Claim
17 words
A protection circuit according to claim 2 in which said auxiliary electrode extends above the semiconductor substrate.
References Cited (Backward Citations)
US4131908A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-10-25 | 1986-04-26 | 1986-10-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-10-25 | 1990-04-26 | 1990-10-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-10-25 | 1994-04-26 | 1994-10-26 | $7700.00 | Window Closed / Lapsed |