Flexible processor on a single semiconductor substrate using a plurality of arrays

Claim 2

A processor fabricated on a single semiconductor substrate comprising: AND array means for receiving program instructions from input sources external of the processor and for generating product signals; OR array means interconnected to said AND array means for receiving said product signals and for generating a plurality of control signals; register means for receiving ones of said plurality of control signals and for transferring data between the processor and data sources external of the processor; arithmetic and logic unit means interconnected to said register means and said OR array means, for executing operations on data received from said register means in accordance with ones of said plurality of control signals and for generating output data; control register means interconnected to said OR array means and said AND array means for receiving ones of said plurality of control signals for controlling execution of said program instructions within said AND array means and; output register means interconnected to receive said output data and ones of said plurality of control signals for buffering said output data between said arithmetic and logic unit means and said data sources external of the processor under control of ones of said plurality of control signals.

Claim 3

The processor of claim 1 wherein said AND array means and said OR array means comprise programmable logic array means.

Claim 4

The processor of claim 2 wherein said programmable logic array means is dynamically programmable.

Claim 5

The processor of claim 1 wherein said control register means controls simultaneous execution of a plurality of said program instructions.

Claim 6

The processor of claim 1 wherein said AND array means receives clock pulses from input sources external of the processor.

Claim 7

The processor of claim 1 wherein said AND array means receives interrupt signals from input sources external of the processor.

Claim 8

The processor of claim 1 wherein the size of said array means are selectively variable.

Claim 9

The processor of claim 1 wherein said semiconductor substrate comprises silicon semiconductor material.

Claim 10

A processor fabricated on a single semiconductor substrate comprising: AND array means for receiving program instructions from input sources external of the processor and for generating product signals; OR array means interconnected to said AND array means for receiving said product signals and for generating a plurality of control signals; register means for receiving ones of said plurality of control signals and for transferring data between the processor and data sources external of the processor; arithmetic and logic unit means interconnected to said register means and said OR array means, for executing operations on data received from said register means in accordance with ones of said plurality of control signals and for generating output data; control register means interconnected to said OR array means and said AND array means for receiving ones of said plurality of control signals for controlling execution of said program instructions within said AND array means; and multiplexer means interconnected to said register means and to data sources external of the processor for controlling flow of data to said register means under control of ones of said plurality of control signals.

Claim 11

A processor fabricated on a single semiconductor substrate comprising: AND array means for receiving program instructions from input sources external of the processor and for generating product signals; OR array means interconnected to said AND array means for receiving said product signals and for generating a plurality of control signals; register means for receiving ones of said plurality of control signals and for transferring data between the processor and data sources external of the processor; arithmetic and logic unit means interconnected to said register means and said OR array means, for executing operations on data received from said register means in accordance with ones of said plurality of control signals and for generating output data; control register means interconnected to said OR array means and said AND array means for receiving ones of said plurality of control signals for controlling execution of said program instructions within said AND array means; and multiplexer means interconnected to said register means and to data sources external of the processor for controlling flow of data to said register means under control of ones of said plurality of control signals.

Claim 12

A processor fabricated on a single semiconductor substrate comprising: AND array means for receiving program instructions from input sources external of the processor and for generating product signals; OR array means interconnected to said AND array means for receiving said product signals and for generating a plurality of control signals; register means for receiving ones of said plurality of control signals and for transferring data between the processor and data sources external of the processor; arithmetic and logic unit means interconnected to said register means and said OR array means, for executing operations on data received from said register means in accordance with ones of said plurality of control signals and for generating output data; control register means interconnected to said OR array means and said AND array means for receiving ones of said plurality of control signals for controlling execution of said program instructions within said AND array means; and code register means interconnected to said arithmetic and logic unit means for storing condition code information generated by said arithmetic and logic unit means for application to said AND array means.

Claim 13

A processor fabricated on a single semiconductor substrate comprising: AND array means for receiving program instructions from input sources external of the processor and for generating product signals; OR array means interconnected to said AND array means for receiving said product signals and for generating a plurality of control signals; register means for receiving ones of said plurality of control signals and for transferring data between the processor and data sources external of the processor; arithmetic and logic unit means interconnected to said register means and said OR array means, for executing operations on data received from said register means in accordance with ones of said plurality of control signals and for generating output data; control register means interconnected to said OR array means and said AND array means for receiving ones of said plurality of control signals for controlling execution of said program instructions within said AND array means; and code register means interconnected to said arithmetic and logic unit means for storing condition code information generated by said arithmetic and logic unit means for application to said AND array means.

Claim 14

A processor fabricated on a single semiconductor substrate comprising: AND array means for receiving program instructions from input sources external of the processor and for generating product signals; OR array means interconnected to said AND array means for receiving said product signals and for generating a plurality of control signals; register means for receiving ones of said plurality of control signals and for transferring data between the processor and data sources external of the processor; arithmetic and logic unit means interconnected to said register means and said OR array means, for executing operations on data received from said register means in accordance with ones of said plurality of control signals and for generating output data; control register means interconnected to said OR array means and said AND array means for receiving ones of said plurality of control signals for controlling execution of said program instructions within said AND array means; and wherein ones of said plurality of control signals are connected from said OR array means to input/output devices external of the processor.

Claim 15

A processor fabricated on a single semiconductor substrate comprising: AND array means for receiving program instructions from input sources external of the processor and for generating product signals; OR array means interconnected to said AND array means for receiving said product signals and for generating a plurality of control signals; register means for receiving ones of said plurality of control signals and for transferring data between the processor and data sources external of the processor; arithmetic and logic unit means interconnected to said register means and said OR array means, for executing operations on data received from said register means in accordance with ones of said plurality of control signals and for generating output data; control register means interconnected to said OR array means and said AND array means for receiving ones of said plurality of control signals for controlling execution of said program instructions within said AND array means; and wherein ones of said plurality of control signals are connected from said OR array means to input/output devices external of the processor.

Claim 16

A processor fabricated on a single semiconductor substrate comprising: AND array means for receiving program instructions from input sources external of the processor and for generating product signals; OR array means interconnected to said AND array means for receiving said product signals and for generating a plurality of control signals; register means for receiving ones of said plurality of control signals and for transferring data between the processor and data sources external of the processor; arithmetic and logic unit means interconnected to said register means and said OR array means, for executing operations on data received from said register means in accordance with ones of said plurality of control signals and for generating output data; control register means interconnected to said OR array means and said AND array means for receiving ones of said plurality of control signals for controlling execution of said program instructions within said AND array means; and said arithmetic and logic unit means comprises programmable logic array means.

Claim 17

A processor fabricated on a single semiconductor substrate comprising: AND array means for receiving program instructions from input sources external of the processor and for generating product signals; OR array means interconnected to said AND array means for receiving said product signals and for generating a plurality of control signals; register means for receiving ones of said plurality of control signals and for transferring data between the processor and data sources external of the processor; arithmetic and logic unit means interconnected to said register means and said OR array means, for executing operations on data received from said register means in accordance with ones of said plurality of control signals and for generating output data; control register means interconnected to said OR array means and said AND array means for receiving ones of said plurality of control signals for controlling execution of said program instructions within said AND array means; and said arithmetic and logic unit means comprises programmable logic array means.

Claim 18

A processor comprising: AND array means for receiving program instructions, clock pulses and interrupt signals from input sources external of the processor and for generating product signals; OR array means interconnected to said AND array means for receiving said product signals and for generating a plurality of control signals; register array means for receiving ones of said plurality of control signals and for transferring data between the processor and data sources external of the processor; arithmetic and logic unit array means interconnected to said register array means and said OR array means for executing operations on data received from said register array means in accordance with ones of said plurality of control signals for generating output data; control register array means interconnected to said OR array means and said AND array means for receiving ones of said plurality of control signals for controlling execution of said program instructions within said AND array means; output register array means interconnected to receive said output data and ones of said plurality of control signals for buffering said output data between said arithmetic and logic unit array means and data sources external of the processor under control of ones of said plurality of control signals; multiplexer register array means interconnected to said register array means and to data sources external of the processor for controlling flow of data to said register array means under control of ones of said plurality of control signals; code register array means interconnected to said arithmetic and logic unit array means for storing code condition information generated by said arithmetic and logic unit array means for application to said AND array means; and all said array means being fabricated on a single semiconductor substrate.

Claim 19

A processor comprising: AND array means for receiving program instructions, clock pulses and interrupt signals from input sources external of the processor and for generating product signals; OR array means interconnected to said AND array means for receiving said product signals and for generating a plurality of control signals; register array means for receiving ones of said plurality of control signals and for transferring data between the processor and data sources external of the processor; arithmetic and logic unit array means interconnected to said register array means and said OR array means for executing operations on data received from said register array means in accordance with ones of said plurality of control signals for generating output data; control register array means interconnected to said OR array means and said AND array means for receiving ones of said plurality of control signals for controlling execution of said program instructions within said AND array means; output register array means interconnected to receive said output data and ones of said plurality of control signals for buffering said output data between said arithmetic and logic unit array means and data sources external of the processor under control of ones of said plurality of control signals; multiplexer register array means interconnected to said register array means and to data sources external of the processor for controlling flow of data to said register array means under control of ones of said plurality of control signals; code register array means interconnected to said arithmetic and logic unit array means for storing code condition information generated by said arithmetic and logic unit array means for application to said AND array means; and all said array means being fabricated on a single semiconductor substrate.

Claim 20

The processor of claim 13 wherein the size of all said array means are selectively variable.

Claim 21

The processor of claim 8 wherein said control register array means controls simultaneous execution of a plurality of said program instructions.

Claim 22

The processor of claim 8 wherein said AND array means and said OR array means are dynamically programmable.

Claim 23

A processor fabricated on a single semiconductor substrate comprising: AND array means for receiving input signals from sources external of the processor and for generating outputs along product signal lines; OR array means disposed adjacent to said AND array means on the semiconductor substrate and interconnected to said product lines for generating control signals along control lines disposed perpendicular to said product lines; register array means disposed adjacent to said OR array means on the semiconductor substrate for receiving said control signals and for generating data along register signal lines; said register signal lines being disposed perpendicular to said control signal lines; arithmetic and logic unit array means disposed adjacent said register array means and said AND array means for receiving said data from said register array means along said register signal lines for generating output data; control register means interconnected to said OR array means and said AND array means for receiving said control signals; and output register means interconnected to receive said output data from said arithmetic and logic unit array means and said control signals for buffering said output data between said arithmetic and logic unit array means and data sources external of the processor under control of said control signals.

Claim 24

A processor fabricated on a single semiconductor substrate comprising: AND array means for receiving input signals from sources external of the processor and for generating outputs along product signal lines; OR array means disposed adjacent to said AND array means on the semiconductor substrate and interconnected to said product lines for generating control signals along control lines disposed perpendicular to said product lines; register array means disposed adjacent to said OR array means on the semiconductor substrate for receiving said control signals and for generating data along register signal lines; said register signal lines being disposed perpendicular to said control signal lines; arithmetic and logic unit array means disposed adjacent said register array means and said AND array means for receiving said data from said register array means along said register signal lines for generating output data; control register means interconnected to said OR array means and said AND array means for receiving said control signals; and output register means interconnected to receive said output data from said arithmetic and logic unit array means and said control signals for buffering said output data between said arithmetic and logic unit array means and data sources external of the processor under control of said control signals.

Claim 25

The processor of claim 17 wherein said product signal lines are disposed parallel to said register signal lines.

Claim 26

The processor of claim 17 wherein said OR array means is disposed laterally adjacent to said AND array means, said register array means is disposed below said OR array means and said arithmetic and logic unit array means is disposed laterally adjacent said register array means and below said AND array means.

Claim 27

A processor fabricated on a single semiconductor substrate for operating on data, said processor comprising: AND array means, responsive to the application thereto of a coded input signal from means external to said substrate, for providing a coded product signal having a coded state related to the code of said input signal, said product signal being provided to product signal conduction paths positioned generally along a linear path on said substrate; said means external to said substrate for applying said coded input signal including clock means; OR array means positioned on said substrate to be connected with said product signal conduction paths for receiving said product signal and generating a coded control signal on control signal conduction paths, the coded state of said control signal being related to the state of said products signal, said control signal conduction paths being positioned generally along a linear path substantially perpendicular to said product signal conduction paths; register array means, positioned on said substrate connected with at least a first portion of said control signal conduction paths, for affecting the reception or provision of said data on data conduction paths in accordance with the state of said control signal on said first portion of said control signal conduction paths, said data conduction paths being positioned generally along a linear path substantially perpendicular to said control signal conduction paths; and output means, positioned on said substrate connected with said data conduction paths and at least a second portion of said control signal conduction paths, for providing data to said data conduction paths from said external means or to said external means from said data conduction paths in accordance with the state of said control signal on said second portion of said control signal conduction paths.

Claim 28

A processor fabricated on a single semiconductor substrate for operating on data, said processor comprising: AND array means, responsive to the application thereto of a coded input signal from means external to said substrate, for providing a coded product signal having a coded state related to the code of said input signal, said product signal being provided to product signal conduction paths positioned generally along a linear path on said substrate; said means external to said substrate for applying said coded input signal including clock means; OR array means positioned on said substrate to be connected with said product signal conduction paths for receiving said product signal and generating a coded control signal on control signal conduction paths, the coded state of said control signal being related to the state of said products signal, said control signal conduction paths being positioned generally along a linear path substantially perpendicular to said product signal conduction paths; register array means, positioned on said substrate connected with at least a first portion of said control signal conduction paths, for affecting the reception or provision of said data on data conduction paths in accordance with the state of said control signal on said first portion of said control signal conduction paths, said data conduction paths being positioned generally along a linear path substantially perpendicular to said control signal conduction paths; and output means, positioned on said substrate connected with said data conduction paths and at least a second portion of said control signal conduction paths, for providing data to said data conduction paths from said external means or to said external means from said data conduction paths in accordance with the state of said control signal on said second portion of said control signal conduction paths.

Claim 29

A processor fabricated on a single semiconductor substrate for operating on data, said processor comprising: AND array means, responsive to the application thereto of a coded input signal from means external to said substrate, for providing a coded product signal having a coded state related to the code of said input signal, said product signal being provided to product signal conduction paths positioned generally along a linear path on said substrate; OR array means positioned on said substrate to be connected with said product signal conduction paths for receiving said product signal and generating a coded control signal on control signal conduction paths, the coded state of said control signal being related to the state of said products signal, said control signal conduction paths being positioned generally along a linear path substantially perpendicular to said product signal conduction paths; register array means, positioned on said substrate connected with at least a first portion of said control signal conduction paths, for affecting the reception or provision of said data on data conduction paths in accordance with the state of said control signal on said first portion of said control signal conduction paths, said data conduction paths being positioned generally along a linear path substantially perpendicular to said control signal conduction paths; output means, positioned on said substrate connected with said data conduction paths and at least a second portion of said control signal conduction paths, for providing data to said data conduction paths from said external means or to said external means from said data conduction paths in accordance with the state of said control signal on said second portion of said control signal conduction paths; and said output means is structured as an array.

Claim 30

A processor fabricated on a single semiconductor substrate for operating on data, said processor comprising: AND array means, responsive to the application thereto of a coded input signal from means external to said substrate, for providing a coded product signal having a coded state related to the code of said input signal, said product signal being provided to product signal conduction paths positioned generally along a linear path on said substrate; OR array means positioned on said substrate to be connected with said product signal conduction paths for receiving said product signal and generating a coded control signal on control signal conduction paths, the coded state of said control signal being related to the state of said products signal, said control signal conduction paths being positioned generally along a linear path substantially perpendicular to said product signal conduction paths; register array means, positioned on said substrate connected with at least a first portion of said control signal conduction paths, for affecting the reception or provision of said data on data conduction paths in accordance with the state of said control signal on said first portion of said control signal conduction paths, said data conduction paths being positioned generally along a linear path substantially perpendicular to said control signal conduction paths; output means, positioned on said substrate connected with said data conduction paths and at least a second portion of said control signal conduction paths, for providing data to said data conduction paths from said external means or to said external means from said data conduction paths in accordance with the state of said control signal on said second portion of said control signal conduction paths; and said output means is structured as an array.

Claim 31

The processor according to claim 21 wherein said AND array and said OR array are programmable to provide a desired coded product signal and coded control signal in response to a given code for said input signal.

Claim 32

The processor according to claim 21 wherein said AND array and said OR array are programmable logic arrays.

Claim 33

The processor according to claim 21 wherein said product signal conduction paths and said data conduction paths are one of metal patterns or diffusion regions and said control signal conduction paths are the other of metal patterns or diffusion regions.

Claim 34

The processor according to claim 21 wherein said processor is self clocking in response to the change in the code of said input signal.

Claim 35

The processor according to claim 21 wherein said input signal includes interrupt signals.

Claim 36

The processor according to claim 21 and further comprising: arithmetic and logic means, positioned on said substrate to be connected with said data conduction paths and at least a third portion of said control signal conduction paths, for performing arithmetic and logical operations on the data applied thereto over said data conduction paths in accordance with the state of said control signal on said third portion of control signal conduction paths, said arithmetic and logic means providing a data signal at an output thereof manifesting the results of the operation performed thereby, said output being connected by a conduction path to said output means, said output means providing the data manifested at the output of said arithmetic and logic means to said register array means or said external means in accordance with the state of said control signal on said second portion of said control signal conduction paths.

Claim 37

The processor according to claim 27 and further comprising: condition code register means connected to and responsive to the operations performed by said arithmetic and logic means for providing signals to said AND array to control the code of the product signal provided thereby, said coded input signals and said condition code register signals being provided to said AND array means along conductive paths positioned on said substrate generally parallel to said control signal paths.

Claim 38

A processor fabricated on a single semiconductor substrate for operating on data, said processor comprising: AND array means, responsive to the application thereto of a coded input signal from means external to said substrate, for providing a coded product signal having a coded state related to the code of said input signal, said product signal being provided to product signal conduction paths positioned generally along a linear path on said substrate; OR array means positioned on said substrate to be connected with said product signal conduction paths for receiving said product signal and generating a coded control signal on control signal conduction paths, the coded state of said control signal being related to the state of said products signal, said control signal conduction paths being positioned generally along a linear path substantially perpendicular to said product signal conduction paths; register array means, positioned on said substrate connected with at least a first portion of said control signal conduction paths, for affecting the reception or provision of said data on data conduction paths in accordance with the state of said control signal on said first portion of said control signal conduction paths, said data conduction paths being positioned generally along a linear path substantially perpendicular to said control signal conduction paths; output means, positioned on said substrate connected with said data conduction paths and at least a second portion of said control signal conduction paths, for providing data to said data conduction paths from said external means or to said external means from said data conduction paths in accordance with the state of said control signal on said second portion of said control signal conduction paths; and controller means, positioned on said substrate to be connected to at least a third portion of said control signal conduction paths, for providing signals to control the code of the product signals provided by said AND array means in accordance with the state of said control signal on said third portion of said control signal conduction paths, said controller means signals being provided along conductive paths positioned between said controller means and said AND array means along a path substantially perpendicular to said product signal conduction paths.

Claim 39

A processor fabricated on a single semiconductor substrate for operating on data, said processor comprising: AND array means, responsive to the application thereto of a coded input signal from means external to said substrate, for providing a coded product signal having a coded state related to the code of said input signal, said product signal being provided to product signal conduction paths positioned generally along a linear path on said substrate; OR array means positioned on said substrate to be connected with said product signal conduction paths for receiving said product signal and generating a coded control signal on control signal conduction paths, the coded state of said control signal being related to the state of said products signal, said control signal conduction paths being positioned generally along a linear path substantially perpendicular to said product signal conduction paths; register array means, positioned on said substrate connected with at least a first portion of said control signal conduction paths, for affecting the reception or provision of said data on data conduction paths in accordance with the state of said control signal on said first portion of said control signal conduction paths, said data conduction paths being positioned generally along a linear path substantially perpendicular to said control signal conduction paths; output means, positioned on said substrate connected with said data conduction paths and at least a second portion of said control signal conduction paths, for providing data to said data conduction paths from said external means or to said external means from said data conduction paths in accordance with the state of said control signal on said second portion of said control signal conduction paths; and controller means, positioned on said substrate to be connected to at least a third portion of said control signal conduction paths, for providing signals to control the code of the product signals provided by said AND array means in accordance with the state of said control signal on said third portion of said control signal conduction paths, said controller means signals being provided along conductive paths positioned between said controller means and said AND array means along a path substantially perpendicular to said product signal conduction paths.

Claim 40

The processor according to claim 28 wherein said coded input signals are provided to said AND array means along conduction paths parallel to said controller means output signal conduction paths.

Claim 41

The processor according to claim 28 wherein said controller means is structured as an array.

Claim 42

A processor fabricated on a single semiconductor substrate for operating on data, said processor comprising: AND array means, responsive to the application thereto of a coded input signal from means external to said substrate, for providing a coded product signal having a coded state related to the code of said input signal, said product signal being provided to product signal conduction paths positioned generally along a linear path on said substrate; OR array means positioned on said substrate to be connected with said product signal conduction paths for receiving said product signal and generating a coded control signal on control signal conduction paths, the coded state of said control signal being related to the state of said products signal, said control signal conduction paths being positioned generally along a linear path substantially perpendicular to said product signal conduction paths; register array means, positioned on said substrate connected with at least a first portion of said control signal conduction paths, for affecting the reception or provision of said data on data conduction paths in accordance with the state of said control signal on said first portion of said control signal conduction paths, said data conduction paths being positioned generally along a linear path substantially perpendicular to said control signal conduction paths; output means, positioned on said substrate connected with said data conduction paths and at least a second portion of said control signal conduction paths, for providing data to said data conduction paths from said external means or to said external means from said data conduction paths in accordance with the state of said control signal on said second portion of said control signal conduction paths; and said output means includes multiplexer means.

Claim 43

A processor fabricated on a single semiconductor substrate for operating on data, said processor comprising: AND array means, responsive to the application thereto of a coded input signal from means external to said substrate, for providing a coded product signal having a coded state related to the code of said input signal, said product signal being provided to product signal conduction paths positioned generally along a linear path on said substrate; OR array means positioned on said substrate to be connected with said product signal conduction paths for receiving said product signal and generating a coded control signal on control signal conduction paths, the coded state of said control signal being related to the state of said products signal, said control signal conduction paths being positioned generally along a linear path substantially perpendicular to said product signal conduction paths; register array means, positioned on said substrate connected with at least a first portion of said control signal conduction paths, for affecting the reception or provision of said data on data conduction paths in accordance with the state of said control signal on said first portion of said control signal conduction paths, said data conduction paths being positioned generally along a linear path substantially perpendicular to said control signal conduction paths; output means, positioned on said substrate connected with said data conduction paths and at least a second portion of said control signal conduction paths, for providing data to said data conduction paths from said external means or to said external means from said data conduction paths in accordance with the state of said control signal on said second portion of said control signal conduction paths; and said output means includes multiplexer means.

Claim 44

The processor according to claim 32 wherein said output means further includes output register means connected to said multiplexer means.

Claim 45

The processor according to claim 33 wherein said multiplexer means and said output register means are structured as arrays.