Digital phase lock loop for TIM frequency

Claim 2

A digital phase-lock loop for effecting programmed changes in the desired output frequency f D of a frequency synthesizer, said output frequency being derived from a reference frequency f S comprising; means defining a synchronizing pulse occurring at a first frequency representative of a predetermined period of a master frequency, means defining a second frequency representative of said output frequency, means for counting bits of said output frequency occurring between a one synchronizing pulse and a subsequent synchronizing pulse to a fixed number and providing an output pulse, and a frequency change monitor to compare the correlation of the output pulse with a synchronizing pulse, and to effect a programmed frequency change of said output frequency f D in said means defining a second frequency in accordance with a predetermined digital logic relationship if and only if, said second frequency differs from said first frequency.

Claim 3

The phase lock loop of claim 1, wherein said frequency change monitor comprises a first flip-flop element producing a first logic correction output signal representative of a high signal for a second frequency higher than said first frequency and a low signal for a second frequency lower than or equal to said first frequency.

Claim 4

The phase lock loop of claim 2, wherein said frequency change monitor further comprises a second flip-flop element producing a second logic correction output signal representative of a high signal for a second frequency lower than said first frequency and a low signal for a second frequency higher than or the equal to said first frequency.

Claim 5

The phase lock loop of claim 3, wherein said frequency change monitor produces a third logic correction output signal representative of a one signal for equal frequency comparison and an opposite signal for an unequal comparison indicating different first and second frequencies.

Claim 6

A digital phase-lock loop for a frequency synthesizer producing a output frequency f D comprising; means producing an output pulse train having a clock frequency f S , a programmable divider receiving an input signal that is a function of f S and dividing said input signal by a number N k which is determined in accordance with: (N E +N R )/N R where, N E is an even number, preferably highest without exceeding f S /f D , and N R is equal to the remainder of (f S /f D )-N E , either a whole number or fraction but not a negative quantity, to produce an output f x , where f x is an even multiple of f D , a second divider receiving the signal f D , and performing a division thereon by a predetermined fixed number and providing a first output indicative of the number of bits counted during a first time base, means providing a second output representative of the number of bits counted during a second time base representative of a master frequency and comparator means receiving said first and second outputs and generating a correction signal which is applied to said programmable divider to adjust the value of N k to synchronize f D with the master frequency.

Claim 7

A digital phase-lock loop for a frequency synthesizer producing a output frequency f D comprising; means producing an output pulse train having a clock frequency f S , a programmable divider receiving an input signal that is a function of f S and dividing said input signal by a number N k which is determined in accordance with: (N E +N R )/N R where, N E is an even number, preferably highest without exceeding f S /f D , and N R is equal to the remainder of (f S /f D )-N E , either a whole number or fraction but not a negative quantity, to produce an output f x , where f x is an even multiple of f D , a second divider receiving the signal f D , and performing a division thereon by a predetermined fixed number and providing a first output indicative of the number of bits counted during a first time base, means providing a second output representative of the number of bits counted during a second time base representative of a master frequency and comparator means receiving said first and second outputs and generating a correction signal which is applied to said programmable divider to adjust the value of N k to synchronize f D with the master frequency.

Claim 8

The phase lock loop of claim 5, wherein said second time base is defined by a synchronizing pulse input to said comparator means.

Claim 9

The phase lock loop of claim 5, wherein said second time base is defined by means of a third divider dividing said master frequency by some predetermined number.

Claim 10

The phase lock loop of claim 7, further comprising logic means receiving said first and second outputs and providing a correction signal to said programmable divider to adjust N k causing the output frequency to synchronize with the master frequency.