High voltage buffer amplifier

Claim 2

An amplifier circuit comprising, in combination: an input impedance matching stage isolated from remaining portions of said circuit; a first amplification stage connected to said impedance matching stage, comprising, in series, an operational amplifier and a transistor; a feedback loop connected between an output of said transistor and an input of said operational amplifier, said feedback loop consisting solely of resistive components; and a second amplification stage connected to said first amplification stage, said second stage comprising an emitter follower transistor network, wherein said second stage is isolated from said operational amplifier.

Claim 3

The circuit of claim 1 wherein said operational amplifier and said two transistors are supplied from a single DC power supply.

Claim 4

The circuit of claim 1 wherein the impedance matching stage consists solely of passive components, and the input impedance of the first amplification stage is much greater than the impedance of the impedance matching stage.

Claim 5

The circuit of claim 1 further comprising an isolation resistance having a fixed value connected between said first amplification stage and said second amplification stage, and a capacitor connected between the transistor of the second amplification stage and an output terminal of said amplifier circuit, wherein said isolation resistance does not affect the frequency response of the circuit.

Claim 6

The circuit of claim 1 wherein the transistor of the first amplification stage provides different amounts of DC and AC gain.

Claim 7

The circuit of claim 5 wherein the DC and AC gains are adjustable independently of each other.

Claim 8

The circuit of claim 6 wherein said DC gainis used to provide the bias to the transistor of the second amplification stage.

Claim 9

The circuit of claim 7 wherein said feedback loop comprises a first resistor having a first terminal connected to the transistor of the first amplification stage, a second resistor connected between a second terminal of said first resistor and ground, and a third resistor connected between said second terminal of said first resistor and an input terminal of said operational amplifier.

Claim 10

The circuit of claim 8 wherein the gain of said first amplification stage is substantially determined by the value of said first and said second resistors.

Claim 11

An amplifier circuit for processing an input signal comprising: An operational amplifier having two inputs and an output; a transistor having only one base, a collector, and an emitter, said base connected to the output of said operational amplifier, said transistor having an AC gain circuit and a DC gain circuit adjustable independently of said AC gain circuit; and a feedback loop connecting the collector of said transistor to one input of said operational amplifier; wherein the input signal is applied to the other input of said operational amplifier; wherein said feedback loop does not affect the gain of said operational amplifier; wherein said feedback loop comprises a pair of voltage dividing resistances R1 and R2 and an over-voltage protection resistance, wherein the overall AC gain of said amplifier circuit is substantially equal to (R1+R2)/R2.

Claim 12

An amplifier circuit for processing an input signal comprising: An operational amplifier having two inputs and an output; a transistor having only one base, a collector, and an emitter, said base connected to the output of said operational amplifier, said transistor having an AC gain circuit and a DC gain circuit adjustable independently of said AC gain circuit; and a feedback loop connecting the collector of said transistor to one input of said operational amplifier; wherein the input signal is applied to the other input of said operational amplifier; wherein said feedback loop does not affect the gain of said operational amplifier; wherein said feedback loop comprises a pair of voltage dividing resistances R1 and R2 and an over-voltage protection resistance, wherein the overall AC gain of said amplifier circuit is substantially equal to (R1+R2)/R2.

Claim 13

The circuit of claim 11 wherein a fourth resistance R4 is connected between the collector of said transistor and a DC power supply voltage; a fifth resistance R5 is connected between the emitter of said transistor and an AC ground; and a sixth resistance R6 is connected between said fifth resistance and a DC ground; wherein the AC gain associated with said transistor is R4/R5; and the DC gain associated with said transistor is R4/(R5+R6).

Claim 14

An amplifier circuit for buffering an input signal comprising: an input terminal to which the signal to be buffered is applied; an input impedance matching network comprising the parallel combination of a capacitor and two series-connected resistors; a signal processing network comprising a series connection of an operational amplifier and a common-emitter NPN transistor having a base, a collector, and an emitter, said signal processing network connected to said impedance matching network via a second capacitor; and a buffer stage connected to said signal processing network via an isolation resistor, said buffer stage including a transistor connected in a common collector configuration, a current biasing resistor, and a blocking capacitor; wherein the power for said operational amplifier and said two transistors is supplied by a common DC source; wherein said operational amplifier is biased by means of two voltage-dividing bias resistors; wherein said processing network contains a feedback loop connecting a collector of said NPN transistor to a noninverting input of said operational amplifier; wherein the collector circuit of said NPN transistor contains a resistance used to impart AC and DC gain to said NPN transistor, and the emitter of said NPN transistor contains a capacitor, a first resistance used to impart AC and DC gain to said NPN transistor, and a second resistance used to impart DC gain but not AC gain to said NPN transistor; wherein said feedback loop contains two voltage-dividing gain-setting resistors and an op-amp-protecting resistor; wherein the AC gain of said signal processing network is substantially determined by the values of said two gain-setting resistors.

Claim 15

An amplifier circuit for buffering an input signal comprising: an input terminal to which the signal to be buffered is applied; an input impedance matching network comprising the parallel combination of a capacitor and two series-connected resistors; a signal processing network comprising a series connection of an operational amplifier and a common-emitter NPN transistor having a base, a collector, and an emitter, said signal processing network connected to said impedance matching network via a second capacitor; and a buffer stage connected to said signal processing network via an isolation resistor, said buffer stage including a transistor connected in a common collector configuration, a current biasing resistor, and a blocking capacitor; wherein the power for said operational amplifier and said two transistors is supplied by a common DC source; wherein said operational amplifier is biased by means of two voltage-dividing bias resistors; wherein said processing network contains a feedback loop connecting a collector of said NPN transistor to a noninverting input of said operational amplifier; wherein the collector circuit of said NPN transistor contains a resistance used to impart AC and DC gain to said NPN transistor, and the emitter of said NPN transistor contains a capacitor, a first resistance used to impart AC and DC gain to said NPN transistor, and a second resistance used to impart DC gain but not AC gain to said NPN transistor; wherein said feedback loop contains two voltage-dividing gain-setting resistors and an op-amp-protecting resistor; wherein the AC gain of said signal processing network is substantially determined by the values of said two gain-setting resistors.