Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
243 words
A device for the synchronized reading of a serial medium which present a series of synchronization words (S), wherein each pair of successive synchronization words is separated by a fixed number of n data words (D0 . . . D7), the synchronization words in undisturbed condition having mutually corresponding bit patterns which differ from the set of allowable data word bit patterns, said device comprising: a. an input (20) for interfacing to said medium; b. a serial buffer memory fed by said input and comprising: b1. a first section (22) for accommodating a synchronization word: b2. an odd number of m (m=1,3 . . . ) serial modules, each module consisting of a second section (24) for accommodating said fixed number of n data words and a third section (26) for accommodating a further synchronization word; b3. an output section (28a) for accommodating a number of p data words, wherein p is the closest integer to the value of n/2, and serially presenting the buffered data words and synchronization words to its output (38); b4. additional memorizing means (28b, 30) for memorizing the occurrence of a synchronization word at said output during an interval corresponding to the length of (n-p) data words plus one synchronization word; c. majority means (32, 34, 36, 40) connected to respective outputs of said first section, said odd number of third sections and said memorizing means for generating a majority signal upon detection of (k+1)/2 synchronization word signals;
Claim 2
Independent Claim
243 words
A device for the synchronized reading of a serial medium which present a series of synchronization words (S), wherein each pair of successive synchronization words is separated by a fixed number of n data words (D0 . . . D7), the synchronization words in undisturbed condition having mutually corresponding bit patterns which differ from the set of allowable data word bit patterns, said device comprising: a. an input (20) for interfacing to said medium; b. a serial buffer memory fed by said input and comprising: b1. a first section (22) for accommodating a synchronization word: b2. an odd number of m (m=1,3 . . . ) serial modules, each module consisting of a second section (24) for accommodating said fixed number of n data words and a third section (26) for accommodating a further synchronization word; b3. an output section (28a) for accommodating a number of p data words, wherein p is the closest integer to the value of n/2, and serially presenting the buffered data words and synchronization words to its output (38); b4. additional memorizing means (28b, 30) for memorizing the occurrence of a synchronization word at said output during an interval corresponding to the length of (n-p) data words plus one synchronization word; c. majority means (32, 34, 36, 40) connected to respective outputs of said first section, said odd number of third sections and said memorizing means for generating a majority signal upon detection of (k+1)/2 synchronization word signals;
Claim 3
Dependent Claim
28 words
d. timing means (152) having a control input connected to said majority means for generating a series-to-parallel control signal for a conversion device (156) fed by said output.
Claim 4
Dependent Claim
28 words
d. timing means (152) having a control input connected to said majority means for generating a series-to-parallel control signal for a conversion device (156) fed by said output.
Claim 5
Dependent Claim
44 words
A device as claimed in claim 1, wherein said majority means comprises a detector for detecting a synchronization word as containing a time interval without a signal value transition that is longer than the maximum allowable value of such interval in the data words.
Claim 6
Dependent Claim
69 words
A device as claimed in claim 1, wherein said memorizing means comprises a delay counter (160) having an input means (34) for detecting a synchronization word in the final one of said m modules, having a delay corresponding to the duration of n data words and one synchronization word, and wherein said majority device decides on (m+1) actually detected synchronization words and an output signal from said delay counter.