US4353091A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for detecting faults in horizontal sync pulse signals
Assignee: Robert Bosch GmbH
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Filing: 1980-12-16
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Granted: 1982-10-05
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Expires: 2000-12-16
Abstract
Abstract To obtain a switching signal whenever a fault occurs in the synchronization signals of a video signal, a fault detection circuit has a counter which receives the signals to be tested at its clock input and reference signals at its control input. The reference signals have the same pulse frequency as the signals to be tested and are obtained from the signals to be tested by a change in keying ratio. The output of the counter is connected in its "clear" input and also, via a monostable flip-flop, to an input from an OR-gate. The other input of the OR-gate receives the reference signals via a diode and an RC-link. The desired switching signal is obtained at the output of the OR-gate.
Inventors
- 👤 Karl-Heinz Hoppe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:28
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/125; H03K5/1252; H04; H04B; H04B1/00; H04B1/06; H04B1/10; H04N; H04N5/00; H04N5/04; H04N5/08; H04N5/14; H04N5/21; H04N5/213
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
186 words
Electrical circuit for detecting faults in a first sequence of pulse signals having a first keying ratio, said circuit including a counter (e) which has a clock input terminal (C) for applying pulse signals of said first sequence, a control input terminal (R) for applying a second sequence of pulse signals having the same pulse frequency as said first sequence and having a second keying ratio which is different from said first keying ratio, an output terminal corresponding to a predetermined count state and a clear terminal (CE) which is connected to said output terminal, a monostable flip-flop (9), an OR-gate (11) having a first OR input terminal, a second OR input terminal, and an OR output terminal, for producing a switching signal upon detection of a fault in said first pulse signals, the output terminal of said counter being connected by means of said flip-flop (9) to said first OR input terminal, an RC-link (7, 8), and a diode (6) for supplying to said RC-link (7, 8) said second sequence of pulse signals, said RC-link (7, 8) being connected to said second OR input terminal.
Claim 2
Dependent Claim
186 words
Electrical circuit for detecting faults in a first sequence of pulse signals having a first keying ratio, said circuit including a counter (e) which has a clock input terminal (C) for applying pulse signals of said first sequence, a control input terminal (R) for applying a second sequence of pulse signals having the same pulse frequency as said first sequence and having a second keying ratio which is different from said first keying ratio, an output terminal corresponding to a predetermined count state and a clear terminal (CE) which is connected to said output terminal, a monostable flip-flop (9), an OR-gate (11) having a first OR input terminal, a second OR input terminal, and an OR output terminal, for producing a switching signal upon detection of a fault in said first pulse signals, the output terminal of said counter being connected by means of said flip-flop (9) to said first OR input terminal, an RC-link (7, 8), and a diode (6) for supplying to said RC-link (7, 8) said second sequence of pulse signals, said RC-link (7, 8) being connected to said second OR input terminal.
Claim 3
Dependent Claim
71 words
Circuit of claim 1 including a bistable flip-flop (12) having a set input terminal (S) which is connected to said OR output terminal, having a clock input terminal (13), and having an output terminal (14) whereby, upon application of vertical synchronization pulse signals to said clock input terminal (13), a switching pulse voltage is produced at said output terminal (14) when a fault occurs in said first sequence of pulse signals.
Claim 4
Dependent Claim
24 words
Circuit of claim 1 including a monostable flip-flop (4) for producing said second sequence of pulse signals from said first sequence of pulse signals.
Claim 5
Dependent Claim
33 words
Circuit of claim 3 in which the time constant of said monostable flip-flop (4) is 75 percent of the pulse period of horizontal synchronization pulse signals in said first sequence of pulse signals.
Claim 6
Dependent Claim
18 words
Circuit of claim 1 in which said predetermined count state of said counter is the count state 2.
Claim 7
Dependent Claim
37 words
Circuit of claim 1 in which the time constant of said monostable flip-flop (9) is greater than or equal to 1.2 times the pulse period of vertical synchronization pulse signals in said first sequence of pulse signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-10-04 | 1986-04-05 | 1986-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-10-04 | 1990-04-05 | 1990-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-10-04 | 1994-04-05 | 1994-10-05 | $7700.00 | Window Closed / Lapsed |