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US4353066A Expired / Lapsed US ⏱️ 0.0 years remaining

Channel switching network

Assignee: Iwasaki Tsushinki KK
•
Filing: 1980-11-25
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Granted: 1982-10-05
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Expires: 2000-11-25
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Abstract

Abstract A channel switching network, in which each cross-point of a switch matrix is constituted as a channel switch of balanced type using two PNPN semiconductor elements. Each of the two PNPN semiconductor elements is arranged in a forward direction with respect to a direct current flowing from the channel switching network to a corresponding terminal equipment. A column of cross-points and a line of cross-points in the switch matrix are designated to select a simultaneously designated cross-point in response to a pair of selection signals. A control circuit is provided for each pair of the incoming lines and the outgoing lines of the switch matrix so that the terminal voltage of a power source for flowing the direct current in the PNPN elements is controlled to temporarily rise to turn ON the PNPN elements at the selected cross-point and thereafter to drop to such a value as only to maintain the PNPN elements in the ON states.

Inventors

  • 👤 Tetsuro Inomata
  • 👤 Kazutada Katsukura
  • 👤 Hikaru Takematsu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 20:45
CPC Classifications
H; H04; H04Q; H04Q3/00; H04Q3/42; H04Q3/52; H04Q3/521

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 212 words
A channel switch network comprising: a plurality of cross-point switches arranged in a switch matrix, each cross-point of which is constituted as a channel switch of balanced type having two PNPN semiconductor elements, each of the two PNPN semiconductor elements being arranged in a forward direction with respect to a direct current flowing from the channel switching network to a corresponding terminal equipment connected to said switch matrix; selection means for designating in response to a pair of selection signals a column of cross-point switches and a line of cross-point switches in the switch matrix to select a simultaneously designated cross-point switch; power source terminal means for receiving a direct current from a power source; and control means provided for each pair of the incoming lines and the outgoing lines of the switch matrix to flow the direct current in the PNPN semiconductor elements at a cross-point of the switch matrix selected by said selection means so that the terminal voltage thereof for flowing the direct current in the selected PNPN semiconductor elements from said power source terminal means is controlled to temporarily rise to turn ON the selected PNPN semiconductor elements and thereafter to drop to a value as to only maintain the selected PNPN semiconductor elements in the ON states.
Claim 2
Dependent Claim 212 words
A channel switch network comprising: a plurality of cross-point switches arranged in a switch matrix, each cross-point of which is constituted as a channel switch of balanced type having two PNPN semiconductor elements, each of the two PNPN semiconductor elements being arranged in a forward direction with respect to a direct current flowing from the channel switching network to a corresponding terminal equipment connected to said switch matrix; selection means for designating in response to a pair of selection signals a column of cross-point switches and a line of cross-point switches in the switch matrix to select a simultaneously designated cross-point switch; power source terminal means for receiving a direct current from a power source; and control means provided for each pair of the incoming lines and the outgoing lines of the switch matrix to flow the direct current in the PNPN semiconductor elements at a cross-point of the switch matrix selected by said selection means so that the terminal voltage thereof for flowing the direct current in the selected PNPN semiconductor elements from said power source terminal means is controlled to temporarily rise to turn ON the selected PNPN semiconductor elements and thereafter to drop to a value as to only maintain the selected PNPN semiconductor elements in the ON states.
Claim 3
Dependent Claim 72 words
A channel switch network according to claim 1, in which said selection means comprises a plurality of line conductors, provided to designate each one of said PNPN semiconductor elements at all cross-points on a line of the switch matrix to be selected, and a plurality of column conductors, provided to designate each the other of said PNPN semiconductor elements at all cross-points on a column of the switch matrix to be selected.
Claim 4
Dependent Claim 133 words
A channel switch network according to claim 1, in which said control means comprises a pair of output terminals for providing said terminal voltage, a first control signal terminal for receiving a first control signal, a second control signal terminal for receiving a second control signal, a current source inserted in a path from one of the terminals of said power source terminal means to one of said pair of output terminal means and controlled to be turned ON in response to said first control signal, and clamping means for clamping the voltage of the other of said pair of output terminals to drop the terminal voltage across said pair of output terminals except when the second control signal is applied at the same time as the designation of said selected cross-point switch.

References Cited (Backward Citations)

US3688051A Cited
US3694812A Cited
US4025726A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1985-10-04 1986-04-05 1986-10-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1989-10-04 1990-04-05 1990-10-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1993-10-04 1994-04-05 1994-10-05 $7700.00 Window Closed / Lapsed

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