Switched-capacitor filter circuit having at least one simulated inductor and having a resonance frequency which is one-sixth of the sampling frequency

Claim 2

A switched-capacitor filter circuit having at least one simulated inductance, said filter circuit operating as the equivalent of a parallel resonance circuit having an inductance L and a capacitance C and having a resonance frequency which is one-sixth of the sampling frequency for the circuit, said circuit comprising: first and second input terminals; a first capacitor; a means for connecting said first capacitor across said input terminals during a first clock phase; a second capacitor; an inverting integration circuit having a feedback capacitor and having an output; a means for connecting said second capacitor to the output of said inverting integration circuit during said first clock phase; a means for transferring a charge from said first capacitor to aid feedback capacitor during a second clock phase; a means for charging said first capacitor by the output of the integration circuit during a third clock phase; a means for connecting said second capacitor across said input terminals during said third clock phase; and a means for transferring a charge from said second capacitor to said feedback capacitor during a fourth clock phase, said first, second, third and fourth clock phases operating in cyclical fashion with non-overlapping duty times at the same clock frequency.

Claim 3

The switched-capacitor filter circuit of clam 1 wherein said clock frequency is equal to one half of said sampling frequency.

Claim 4

The switched-capacitor filter circuit of clam 1 wherein said clock frequency is equal to one half of said sampling frequency.

Claim 5

The switched-capacitor filter circuit of claim 1 wherein said first, second and feedback capacitors each have the same capacitance value.

Claim 6

The switched-capacitor filter circuit of claim 3 wherein said capacitance value is equal to C+T 2 /4L, where T is the sampling period which is the reciprocal of said sampling frequency.

Claim 7

The switched-capacitor filter circuit of claim 1 wherein said first capacitor, said second capacitor and said inverting integration circuit are each connected to said second terminal, said second terminal being connected to a reference potential for operating said filter circuit as a grounded parallel resonance circuit.

Claim 8

The electronic filter circuit of claim 1 wherein said first and second capacitors are connected to a reference potential and further comprising: a means for disconnecting said first capacitor from said reference potential and simultaneously connecting said first capacitor to said second terminal during said first clock phase; and a means for disconnecting said second capacitor from said reference potential and simultaneously connecting said second capacitor to said second terminal during said third clock phase for operating said filter circuit as a floating parallel resonance circuit.

Claim 9

The switched-capacitor filter circuit of claim 1 further comprising: at least one additional capacitor; a means for alternately connecting said additional capacitor across said input terminals and to the output of said integration circuit; a means for transferring a charge from said additional capacitor to said feedback capacitor; and wherein said sampling frequency is equal to (2 +n) times said clock frequency where n is the number of additional capacitors.

Claim 10

The switched-capacitor filter circuit of claim 1 consists of an operational amplifier having an output which is said output of the inverting integration circuit, said operational amplifier having an inverting input and said feedback capacitor being interconnected between the output and inverting input of said operational amplifier, said inverting input of said operational amplifier serving as the input for said inverting integration circuit, and said operational amplifier having a non-inverting input connected to a reference potential.

Claim 11

The switched-capacitor filter circuit of claim 7 wherein said second input terminal is connected to a reference potential and wherein said first capacitor is interconnected between said second input terminal and a first circuit node and said second capacitor is interconected between said second input terminal and a second circuit node and wherein said means for connecting said first capacitor across said input terminals is a first switch which is closed during said first clock phase interconnected between said first input terminal and said first circuit node, said means for connecting said second capacitor across said input terminals is a second switch which is closed during said third clock phase interconnected between said first input terminal and said second circuit node, said means for connecting said second capacitor to the output of said inverting integration circuit is a third switch which is closed during said first clock phase interconnected between said integration circuit output and said second circuit node, said means for charging said first capacitor by the output of the integration circuit is a fourth switch which is closed during said third clock phase interconnected between said integration circuit output and said first circuit node, said means for transferring a charge from said first capacitor to said feedback capacitor is a fifth switch which is closed during said second clock phase interconnected between said input of said integration circuit and said first circuit node, and said means for transferring a charge from said second capacitor to said feedback capacitor is a sixth switch which is closed during said fourth clock phase interconnected between said integration circuit input and said second circuit node.

Claim 12

The switched-capacitor filter circuit of claim 9 wherein said filter circuit has a third circuit node disposed between said first capacitor and said second terminal and said reference potential, and a fourth circuit node disposed between said second capacitor and said second input terminal and said reference potential, and further comprising: a seventh switch which is closed during said third clock phase interconnected between said fourth circuit node and said second input terminal; an eighth switch which is closed during said first clock phase interconnected between said third circuit node and said second input terminal; a ninth switch which is closed during said first and said fourth clock phases interconnected between said fourth circuit node and the refrence potential; and a tenth switch which is closed during said second and said third clock phases interconnected between said third circuit node and the reference potential, for operating said switched-capacitor filter circuit as a floating parallel resonance circuit.

Claim 13

A switched-capacitor filter circuit having at least one simulated inductance, said filter circuit operating as the equivalent of a parallel resonance circuit having an inductance L and a capacitance C and having a resonance frequency which is one-sixth of the sampling frequency for the filter circuit, said circuit comprising: first and second input terminals; a first capacitor interconnected between first and third circuit nodes; a second capacitor interconected between second and fourth circuit nodes; at least one additional capacitor interconnected between fifth and sixth circuit nodes; an inverting integration circuit including an operational amplifier having inverting and non-inverting inputs and an output, a feedback capacitor interconnected between the output and the inverting input of the amplifier, said output of said amplifier serving as the output of said integration circuit and the inverting input of said amplifier serving as the input for said integration circuit, and said non-inverting input being connected to a reference potential; a first switch interconnected between said first node and said first input terminal; a second switch interconnected between said second node and said first input terminal; a third switch interconnected between the output of said integration circuit and said first node; a fourth switch interconnected between the output of said integration circuit and the second node; a fifth switch interconnected between the input of said integration circuit and said first node; a sixth switch interconnected between the input of said integration circuit and said second node; a seventh switch interconnected between said second input terminal and said fourth node; an eighth switch interconnected between said second input terminal and said third node; a ninth switch interconnected between said fourth node and said reference potential; a tenth switch interconnected between said third node and said reference potential; an eleventh switch interconnected between said first input terminal and said fifth node; a twelfth switch interconnected between said fifth node and said input of said integration circuit; a thirteenth switch interconnected between the second input terminal and said sixth node; a fourteenth switch interconected between said sixth node and said reference potential; and a fifteenth switch interconnected between said fifth node and the output of said integration circuit, said first, fourth, eighth, and twelfth switches being closed during a first clock phase, said second, fifth, seventh, and fifteenth switches being closed during a second clock phase, said third, sixth, eleventh, and thirteenth switches being closed during a third clock phase, said ninth switch being closed during said first and third clock phases, said tenth switch being closed during said second and third clock phases, and said fourteenth switch being closed during said first and second clock phases, said clock phases operating in cyclical fashion with non-overlapping duty times at the same clock frequency.

Claim 14

A switched-capacitor filter circuit having at least one simulated inductance, said filter circuit operating as the equivalent of a parallel resonance circuit having an inductance L and a capacitance C and having a resonance frequency which is one-sixth of the sampling frequency for the filter circuit, said circuit comprising: first and second input terminals; a first capacitor interconnected between first and third circuit nodes; a second capacitor interconected between second and fourth circuit nodes; at least one additional capacitor interconnected between fifth and sixth circuit nodes; an inverting integration circuit including an operational amplifier having inverting and non-inverting inputs and an output, a feedback capacitor interconnected between the output and the inverting input of the amplifier, said output of said amplifier serving as the output of said integration circuit and the inverting input of said amplifier serving as the input for said integration circuit, and said non-inverting input being connected to a reference potential; a first switch interconnected between said first node and said first input terminal; a second switch interconnected between said second node and said first input terminal; a third switch interconnected between the output of said integration circuit and said first node; a fourth switch interconnected between the output of said integration circuit and the second node; a fifth switch interconnected between the input of said integration circuit and said first node; a sixth switch interconnected between the input of said integration circuit and said second node; a seventh switch interconnected between said second input terminal and said fourth node; an eighth switch interconnected between said second input terminal and said third node; a ninth switch interconnected between said fourth node and said reference potential; a tenth switch interconnected between said third node and said reference potential; an eleventh switch interconnected between said first input terminal and said fifth node; a twelfth switch interconnected between said fifth node and said input of said integration circuit; a thirteenth switch interconnected between the second input terminal and said sixth node; a fourteenth switch interconected between said sixth node and said reference potential; and a fifteenth switch interconnected between said fifth node and the output of said integration circuit, said first, fourth, eighth, and twelfth switches being closed during a first clock phase, said second, fifth, seventh, and fifteenth switches being closed during a second clock phase, said third, sixth, eleventh, and thirteenth switches being closed during a third clock phase, said ninth switch being closed during said first and third clock phases, said tenth switch being closed during said second and third clock phases, and said fourteenth switch being closed during said first and second clock phases, said clock phases operating in cyclical fashion with non-overlapping duty times at the same clock frequency.

Claim 15

The switched-capacitor filter circuit of claim 11 wherein each of said capacitors has the same capacitance value.

Claim 16

The switched-capacitor filter circuit of claim 12 wherein said capacitance value is equal to C+T 2 /4L, where T is the sampling period which is equal to the reciprocal of the sampling frequency.

Claim 17

The switched-capacitor filter circuit of claim 11 wherein said clock frequency is equal to 1/(2+n) times the sampling frequency where n is the number of additional capacitors.