US4352152A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed non-saturating inverter
Assignee: HYBRICON Inc
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Filing: 1980-01-11
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Granted: 1982-09-28
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Expires: 2000-01-11
Abstract
Abstract Method and apparatus are disclosed herein for controlling the voltage supplied to a motor to vary the speed thereof. A pulsewidth modulator is supplied a sawtooth waveform from a waveform generator and is controlled by an input signal to provide a variable duty cycle pulse train. The waveform generator also provides a start pulse which triggers an output driver circuit. The output driver circuit provides base current to a plurality of paralleled output transistor stages, which may be Darlington pairs, connected to the motor. The collector voltage of the output stages is monitored and, if it drops below a predetermined threshold at the edge of saturation, is clamped to a voltage and the edge of saturation, thereby preventing the output transistors from operating in saturation while at the same time minimizing the voltage across the collector of the output stages. This arrangement eliminates the need for emitter resistors while at the same time providing for high speed operation and better load sharing among the paralleled output transistors.
Inventors
- 👤 Stephen H. Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:19
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/53; H02M7/537; H02M7/539
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
110 words
Apparatus for generating a variable duty cycle pulse train comprising means adapted to receive a control signal, sawtooth generator means for supplying a sawtooth waveform, first amplifier means responsive to said control signal for establishing a reference voltage in accordance with the amplitude of said control signal, and open loop amplifier means responsive to said reference voltage and said sawtooth generator means for generating a train of pulses, the value of said reference voltage establishing the duty cycle of said pulse train, said open loop amplifier means including means for providing positive feedback of a substantially smaller amplitude than the amplitude of the output of said open loop amplifier means.
Claim 2
Dependent Claim
110 words
Apparatus for generating a variable duty cycle pulse train comprising means adapted to receive a control signal, sawtooth generator means for supplying a sawtooth waveform, first amplifier means responsive to said control signal for establishing a reference voltage in accordance with the amplitude of said control signal, and open loop amplifier means responsive to said reference voltage and said sawtooth generator means for generating a train of pulses, the value of said reference voltage establishing the duty cycle of said pulse train, said open loop amplifier means including means for providing positive feedback of a substantially smaller amplitude than the amplitude of the output of said open loop amplifier means.
Claim 3
Dependent Claim
104 words
An improved variable pulsewidth inverter comprising: first means adapted to be responsive to a control signal for generating a train of pulses, the pulsewidth of said pulses varying in accordance with the control signal, said pulsewidth defining a duty cycle of said pulses, output means responsive to said train of pulses adapted for supplying power to a load according to said duty cycle, and current limiting means responsive to the condition of said output means for controlling said output means to limit current through said output means in accordance with a predetermined current limit, said predetermined current limit tapering according to said duty cycle.
Claim 4
Dependent Claim
104 words
An improved variable pulsewidth inverter comprising: first means adapted to be responsive to a control signal for generating a train of pulses, the pulsewidth of said pulses varying in accordance with the control signal, said pulsewidth defining a duty cycle of said pulses, output means responsive to said train of pulses adapted for supplying power to a load according to said duty cycle, and current limiting means responsive to the condition of said output means for controlling said output means to limit current through said output means in accordance with a predetermined current limit, said predetermined current limit tapering according to said duty cycle.
Claim 5
Dependent Claim
16 words
The variable pulsewidth inverter of claim 2 wherein said tapering occurs during each of said pulses.
Claim 6
Dependent Claim
26 words
The variable pulsewidth inverter of claim 3 wherein said current limiting means is further responsive to said first means for synchronizing said tapering with said pulses.
Claim 7
Dependent Claim
145 words
An improved variable pulsewidth inverter comprising: first means adapted to be responsive to a control signal for generating a train of pulses, the pulsewidth of said pulses varying in accordance with the control signal, said pulsewidth defining a duty cycle of said pulses, output means responsive to said train of pulses adapted for applying power to a load in accordance with said duty cycle, and current limit means responsive to the condition of said output means, said condition indicative of current flowing through said output means, for controlling said output means to limit the current through said output means in accordance with a tapering predetermined current limit, said current limit tapering during each pulse of said train of pulses, said current limit means being responsive to said first means to synchronize said tapering of the current limit with each pulse of said train of pulses.
Claim 8
Dependent Claim
145 words
An improved variable pulsewidth inverter comprising: first means adapted to be responsive to a control signal for generating a train of pulses, the pulsewidth of said pulses varying in accordance with the control signal, said pulsewidth defining a duty cycle of said pulses, output means responsive to said train of pulses adapted for applying power to a load in accordance with said duty cycle, and current limit means responsive to the condition of said output means, said condition indicative of current flowing through said output means, for controlling said output means to limit the current through said output means in accordance with a tapering predetermined current limit, said current limit tapering during each pulse of said train of pulses, said current limit means being responsive to said first means to synchronize said tapering of the current limit with each pulse of said train of pulses.
Claim 9
Dependent Claim
159 words
An improved variable pulsewidth inverter comprising: first means adapted to be responsive to a control signal for generating a train of pulses, the pulsewidth of said pulses varying in accordance with the control signal, said pulsewidth defining a duty cycle of said pulses, output means including at least one transistor having a collector, said output means being for controlling the conduction of said at least one transistor in response to said pulses, said at least one transistor being adapted to be connected to a load, and current limiting means responsive to said collector for controlling said output means to limit current flow through said at least one transistor in response to a tapering current limit, said current limiting means being responsive to said first means for synchronizing said tapering current limit with each said pulse, the magnitude of said tapering for respective ones of said pulses varying in accordance with the pulsewidth of said respective ones of said pulses.
Claim 10
Dependent Claim
159 words
An improved variable pulsewidth inverter comprising: first means adapted to be responsive to a control signal for generating a train of pulses, the pulsewidth of said pulses varying in accordance with the control signal, said pulsewidth defining a duty cycle of said pulses, output means including at least one transistor having a collector, said output means being for controlling the conduction of said at least one transistor in response to said pulses, said at least one transistor being adapted to be connected to a load, and current limiting means responsive to said collector for controlling said output means to limit current flow through said at least one transistor in response to a tapering current limit, said current limiting means being responsive to said first means for synchronizing said tapering current limit with each said pulse, the magnitude of said tapering for respective ones of said pulses varying in accordance with the pulsewidth of said respective ones of said pulses.
Claim 11
Dependent Claim
57 words
The improved variable pulsewidth inverter of claim 6 wherein said first means includes ramp generator means for generating a ramp signal having a rise time and a fall time substantially shorter than said rise time, and said current limiting means being responsive to at least a portion of said ramp signal to provide said tapering current limit.
Claim 12
Dependent Claim
34 words
An improved variable pulsewidth inverter as in claim 7 wherein said first means further includes comparator means for comparing said ramp signal with said control signal, said comparator means generating said train of pulses.
Claim 13
Dependent Claim
31 words
The improved variable pulsewidth inverter of claim 6 wherein said current limiting means is further for controlling said output means for preventing said at least one transistor from operating in saturation.
Claim 14
Independent Claim
82 words
A method for limiting current flow in a variable pulsewidth inverter, comprising the steps of generating a train of pulses in response to a control signal, the pulsewidth of said pulses varying in accordance with the control signal, said pulsewidth defining a duty cycle of said pulses, supplying current to a load according to said duty cycle, and limiting the current supplied to said load in accordance with a predetermined current limit, said predetermined current limit tapering according to said duty cycle.
Claim 15
Independent Claim
82 words
A method for limiting current flow in a variable pulsewidth inverter, comprising the steps of generating a train of pulses in response to a control signal, the pulsewidth of said pulses varying in accordance with the control signal, said pulsewidth defining a duty cycle of said pulses, supplying current to a load according to said duty cycle, and limiting the current supplied to said load in accordance with a predetermined current limit, said predetermined current limit tapering according to said duty cycle.
Claim 16
Dependent Claim
15 words
The method as in claim 10 wherein said tapering occurs during each of said pulses.
Claim 17
Dependent Claim
20 words
The method of claim 11 wherein the current limiting step further includes sychronizing said tapering with each of said pulses.
Claim 18
Independent Claim
91 words
A method for limiting current in a variable pulsewidth inverter comprising the steps of generating a train of pulses, the pulsewidth of said pulses varying in accordance with a control signal, said pulsewidth defining a duty cycle of said pulses applying current to a load in accordance with said duty cycle, limiting current to said load in accordance with a tapering predetermined current limit, said current limit tapering during each pulse of said train of pulses, and synchronizing said tapering predetermined current limit with each pulse of said train of pulses.
Claim 19
Independent Claim
91 words
A method for limiting current in a variable pulsewidth inverter comprising the steps of generating a train of pulses, the pulsewidth of said pulses varying in accordance with a control signal, said pulsewidth defining a duty cycle of said pulses applying current to a load in accordance with said duty cycle, limiting current to said load in accordance with a tapering predetermined current limit, said current limit tapering during each pulse of said train of pulses, and synchronizing said tapering predetermined current limit with each pulse of said train of pulses.
Claim 20
Independent Claim
125 words
A method for limiting current flow in a variable pulsewidth inverter comprising the steps of generating a train of pulses, the pulsewidth of said pulses varying in accordance with a control signal, said pulsewidth defining a duty cycle of said pulses, controlling the conduction of at least one transistor in response to said pulses, said at least one transistor having a collector and being adapted to be connected to a load, controlling said transistor to limit current flow through said at least one transistor in response to a tapering current limit, and synchronizing said tapering current limit with each said pulse, the magnitude of said tapering for respective ones of said pulses varying in accordance with the pulsewidth of said respective ones of said pulses.
Claim 21
Independent Claim
125 words
A method for limiting current flow in a variable pulsewidth inverter comprising the steps of generating a train of pulses, the pulsewidth of said pulses varying in accordance with a control signal, said pulsewidth defining a duty cycle of said pulses, controlling the conduction of at least one transistor in response to said pulses, said at least one transistor having a collector and being adapted to be connected to a load, controlling said transistor to limit current flow through said at least one transistor in response to a tapering current limit, and synchronizing said tapering current limit with each said pulse, the magnitude of said tapering for respective ones of said pulses varying in accordance with the pulsewidth of said respective ones of said pulses.
Claim 22
Dependent Claim
48 words
A method as in claim 14 wherein the method includes the additional steps of generating a ramp signal having a rise time and a fall time substantially shorter than said rise time, and tapering said current limit at least in response to a portion of said ramp signal.
Claim 23
Dependent Claim
35 words
A method as in claim 15 wherein said generating steps includes the additional step of comparing said ramp signal with said control signal and generating said train of pulses in response to said comparing step.
Claim 24
Dependent Claim
28 words
A method as in claim 14 including the additional step of controlling said at least one transistor for preventing said at least one transistor from operating in saturation.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-09-27 | 1986-03-29 | 1986-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-09-27 | 1990-03-29 | 1990-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-09-27 | 1994-03-29 | 1994-09-28 | $7700.00 | Window Closed / Lapsed |