Precharge circuit

Claim 2

In combination with N separate circuits, where N is an integer greater than 2, each circuit being connected between a different one of N output points and a common point, animproved precharge circuit for selectively and concurrently placing said N output points at, or close to, a selected operating potential, comprising: N-1 transistors, each transistor having a conduction path and a control electrode; means connecting the conductin paths of each one of said N-1 transistors between two, different ones, of said N output points, whereby the conduction paths of said N-1 transistors are connected end-to-end in series; an additional transistor having its conduction path connected between one of said N output points and a point of operating potential; and means connected to the control electrodes of said N-1 transistors and to the control electrode of said additional transistor for selectively turning them on concurrently and distributing the potential at said point of operating potential to said N output points.

Claim 3

The combination as claimed in claim 1 wherein said N separate circuits are formed on an integrated circuit, each one of said N output points being spaced apart on said integrated circuit, and wherein the conduction path of each one of said N-1 transistors is formed between a different pair of said N output points.

Claim 4

The combination as claimed in claim 2 wherein said N separate circuits are formed by and include transistors of one conductivity type; further including a control transistor of said one conductivity type having its conduction path connected between said common point and a point of reference potential; and wherein said N-1 transistors and said additional transistor are of opposite conductivity type to said one conductivity type.

Claim 5

The combination as claimed in claim 3 further including means for selectively and concurrently turning off said control transistor when said precharge transistors are turned-on and turning-on said control transistor when said precharge transistors are turned off.

Claim 6

An integrated field-effect transistor circuit comprising: a semiconductor body of first conductivity type; X logic circuits formed in said body, each logic circuit having an output and comprising a plurality of transistors, each transistor having a conduction path and a control electrode, the conduction paths of the transistors of each one of said X logic circuits being connected in circuit between its output and a common line, where X is an integer greater than 2; X spaced apart output lines, one line per output, each line being physically displaced from its corresponding output, said lines being of conductive material and being isolated from and overlying said semiconductor body and extending in a first direction; X spaced apart regions of second conductivity type; each one of said X regions being formed in said body between a different one of said outputs and a different one of said output lines, each one of said X spaced apart regions being connected at one end to its corresponding output and at its other end to its corresponding output line for providing a continuous signal propagation path between its corresponding output and its corresponding output line along said first direction, and said X spaced apart regions forming the source and drain regions of precharge transistors whose conduction paths are in a direction orthogonal to said first direction; a conductor isolated from and overlying said X regions extending in a direction orthogonal to said first direction for forming the control electrodes of said precharge transistors; means for applying a predetermined potential, in reference to said body, to one of said X spaced apart regions; and means for applying a signal to said conductor for selectively causing conduction between said X regions and placing said X regions and their conduction paths at said predetermined potential for a selected period of time.

Claim 7

An integrated field-effect transistor circuit comprising: a semiconductor body of first conductivity type; X logic circuits formed in said body, each logic circuit having an output and comprising a plurality of transistors, each transistor having a conduction path and a control electrode, the conduction paths of the transistors of each one of said X logic circuits being connected in circuit between its output and a common line, where X is an integer greater than 2; X spaced apart output lines, one line per output, each line being physically displaced from its corresponding output, said lines being of conductive material and being isolated from and overlying said semiconductor body and extending in a first direction; X spaced apart regions of second conductivity type; each one of said X regions being formed in said body between a different one of said outputs and a different one of said output lines, each one of said X spaced apart regions being connected at one end to its corresponding output and at its other end to its corresponding output line for providing a continuous signal propagation path between its corresponding output and its corresponding output line along said first direction, and said X spaced apart regions forming the source and drain regions of precharge transistors whose conduction paths are in a direction orthogonal to said first direction; a conductor isolated from and overlying said X regions extending in a direction orthogonal to said first direction for forming the control electrodes of said precharge transistors; means for applying a predetermined potential, in reference to said body, to one of said X spaced apart regions; and means for applying a signal to said conductor for selectively causing conduction between said X regions and placing said X regions and their conduction paths at said predetermined potential for a selected period of time.

Claim 8

The combination as claimed in claim 5 wherein said semiconductor body is a substrate of said first conductivity type; wherein said first and second conductivity types are complementary to each other; wherein the transistors of said X logic circuits are formed in a well-region of said second conductivity type formed in said body; said transistors of said X logic circuits having source and drain regions of first conductivity type formed in said well-region, said logic transistors being of said first conductivity type; and wherein said precharge transistors are transistors of second conductivity type.

Claim 9

The combination as claimed in claim 6 wherein the conduction paths of the transistors of each one of said X logic circuits are connected in series between its output and said common line, and wherein the conduction paths of the transistors of each one of said X logic circuits is in line with its corresponding one of said X spaced apart region and its corresponding output line.

Claim 10

The combination as claimed in claim 6 further including means coupled to said X logic circuits for preventing the flow of direct current through the transistors in said X logic circuits when said precharge transistors are turned on.

Claim 11

An integrated circuit comprising: a substrate of one conductivity type; a plurality of X integrated circuits, each terminating in a first output region, respectively, said first output regions being spaced from one another along a line extending in a column direction, where X is an integer greater than 2; X second output regions, one second output region per first output region, each one of said second output regions being formed in said substrate and being of opposite conductivity type to the conductivity of said substrate, each one of said second output regions being spaced apart from its corresponding first region, in a row direction which is orthogonal to said column direction, said second output regions being spaced apart from one another along a line extending in said column direction, each said second output region serving as at least one of the source and drain regions of a group of transistors and pairs of adjacent ones of said second output regions serving as the source and drain regions, respectively, of the transistors of said group; a common conductor serving as the common gate electrode of all the transistors of said group, said conductor being insulated from the substrate and extending in said first column direction over said second output regions; and X conductors each joining a first output region to its corresponding second output region in the same row, said X second output regions also serving as X circuit output points.

Claim 12

An integrated circuit comprising: a substrate of one conductivity type; a plurality of X integrated circuits, each terminating in a first output region, respectively, said first output regions being spaced from one another along a line extending in a column direction, where X is an integer greater than 2; X second output regions, one second output region per first output region, each one of said second output regions being formed in said substrate and being of opposite conductivity type to the conductivity of said substrate, each one of said second output regions being spaced apart from its corresponding first region, in a row direction which is orthogonal to said column direction, said second output regions being spaced apart from one another along a line extending in said column direction, each said second output region serving as at least one of the source and drain regions of a group of transistors and pairs of adjacent ones of said second output regions serving as the source and drain regions, respectively, of the transistors of said group; a common conductor serving as the common gate electrode of all the transistors of said group, said conductor being insulated from the substrate and extending in said first column direction over said second output regions; and X conductors each joining a first output region to its corresponding second output region in the same row, said X second output regions also serving as X circuit output points.