Time of day clock control

Claim 2

In a computer system having a time of day clock which is synchronized with a system clock by stepping the time of day clock at two different rates to synthesize fractional relationships between the periods of the time of day clock and the system clock the method comprising: using a single oscillating source for both the time of day clock and the system clock, and selecting the system clock cycle T such that a binary multiple N of the time of day clock cycle D contains an integral number, K, of processor cycles, T, or ND=KT in accordance with the equation: D=(R±X/N)T, where R is the integer nearest the actual D/T ratio and X represents the number of time of day clock cycles D of longer or shorter duration than R processor cycles needed to establish the fractional relationship between the two cycles over the period ND.

Claim 3

The computer system of claim 1 including selecting the binary multiple N as a function of the processor cycle time T accuracy ΔT/T in accordance with the following formual: ##EQU4##

Claim 4

In a computer system having a time of day clock register run off a system clock by stepping the time of day clock register at two different rates to synthesize fractional relationship between the time of day clock period D and the system clock period T, the improvement comprising: counting means for counting the number of pulses produced by the system clock, binary comparator means for resetting said counter to 0 and incrementing the time of day register when it produces a compare signal, logic circuit means responsive to binary counts in a number of stages of the register for feeding one binary number into said comparator on certain binary counts and another binary number into the register on other binary counts, and circuit means for periodically feeding the contents of said counting means into said comparator for comparison with one of said binary numbers to produce said compare signal when said contents is equal to the one of said binary numbers, whereby the time of day register is incremented at one rate when said one binary number is fed into said comparator and another rate when said other binary number is fed into said comparator.

Claim 5

In a computer system having a time of day clock register run off a system clock by stepping the time of day clock register at two different rates to synthesize fractional relationship between the time of day clock period D and the system clock period T, the improvement comprising: counting means for counting the number of pulses produced by the system clock, binary comparator means for resetting said counter to 0 and incrementing the time of day register when it produces a compare signal, logic circuit means responsive to binary counts in a number of stages of the register for feeding one binary number into said comparator on certain binary counts and another binary number into the register on other binary counts, and circuit means for periodically feeding the contents of said counting means into said comparator for comparison with one of said binary numbers to produce said compare signal when said contents is equal to the one of said binary numbers, whereby the time of day register is incremented at one rate when said one binary number is fed into said comparator and another rate when said other binary number is fed into said comparator.