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US4349871A
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Duplicate tag store for cached multiprocessor system
Assignee: Digital Equipment Corp
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Filing: 1980-01-28
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Granted: 1982-09-14
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Expires: 2000-01-28
Abstract
Abstract A cached multiprocessor system operated in an ordered pipeline timing sequence in which the time slot for use of the cache is made long enough to permit only one cache access. Further, the time slot for data transfers to and from the processors succeeds the time slot for accessing the cache. The sequence is optimized for transactions that require only one cache access, e.g., read operations that hit the cacgenerally require a second cache access in order to update or allocate the cache. These transactions are entered into a queue with order preserved prior to permitting a second access to the cache. Also, a duplicate tag store is associated with the queue and maintained as a copy of the tag store in the cache. Whenever a cache tag is to be changed, a duplicate tag in the duplicate tag store is changed prior to changing the cache tag. The duplicate tag store thus always provides an accurate indication of the contents of the cache. The duplicate tag store is used to determine whether a second access to the cache for an update is necessary.
Inventors
- 👤 Richard F. Lary
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:10
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/084
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
488 words
A multiprocessor system comprising: A. main memory means (18) including a plurality of addressable storage locations for storing data and for generating address, data and memory control signals; B. A plurality of processor units (22) for processing data in response to instructions and for generating signals including address, data, and writing control signals for initiating transactions that access addressable storage locations in said main memory means; C. common control means shared by said processor units and said main memory means, said common control means including i. receiving means (24) for receiving said address, memory control, writing control, and data signals from said processor units and said main memory means, ii. write-through cache memory means (20) including a plurality of addressable storage locations each having a tag portion (20A) for storing a tag address that identifies a certain location in said main memory means and a corresponding data portion (20B) for storing a copy of the data stored in that location of said main memory means, said cache memory means further including updating means connected to said receiving means and responsive to said writing control signal for forgoing the writing of data signals into the data portion thereof and responsive to said memory control signal for writing the data portion of said cache memory means corresponding to an address in the main memory means; iii. transmitting means (38) connected to said receiving means for transmitting said address, writing control, and data signals to said main memory means; D. processor bus means (P-Bus) interconnecting said processor units and said common control means for transferring said address, writing control and data signals associated with the transactions among said processor units and said common control means; E. memory bus means (60) interconnecting said common control means and said main memory means for transferring said address, writing control, memory control, and data signals associated with the transactions between said common control means and said memory means; and F. said common control means further including: ii. first queing means (70) interposed between said transmitting means and said memory bus means for receiving said address, writing control and data signals and for subsequently transmitting said signals to said memory bus means; iii. duplicate tag storage means (86) connected to said cache memory means for maintaining copies of the tag address information stored in the tag portion of said cache memory means; and iv. second queing means (80) connected to said duplicate tag storage means and being interposed between said memory bus means and said receiving means for receiving on a first-in-first out basis said address, memory control and data signals from said main memory means, said second queing means being operative to subsequently transmit to said receiving means said address, memory control, and data signals when said address signal matches an address contained in said duplicate tag storage means thereby to enable said updating means to write the data portion of said cache memory means.
Claim 2
Dependent Claim
488 words
A multiprocessor system comprising: A. main memory means (18) including a plurality of addressable storage locations for storing data and for generating address, data and memory control signals; B. A plurality of processor units (22) for processing data in response to instructions and for generating signals including address, data, and writing control signals for initiating transactions that access addressable storage locations in said main memory means; C. common control means shared by said processor units and said main memory means, said common control means including i. receiving means (24) for receiving said address, memory control, writing control, and data signals from said processor units and said main memory means, ii. write-through cache memory means (20) including a plurality of addressable storage locations each having a tag portion (20A) for storing a tag address that identifies a certain location in said main memory means and a corresponding data portion (20B) for storing a copy of the data stored in that location of said main memory means, said cache memory means further including updating means connected to said receiving means and responsive to said writing control signal for forgoing the writing of data signals into the data portion thereof and responsive to said memory control signal for writing the data portion of said cache memory means corresponding to an address in the main memory means; iii. transmitting means (38) connected to said receiving means for transmitting said address, writing control, and data signals to said main memory means; D. processor bus means (P-Bus) interconnecting said processor units and said common control means for transferring said address, writing control and data signals associated with the transactions among said processor units and said common control means; E. memory bus means (60) interconnecting said common control means and said main memory means for transferring said address, writing control, memory control, and data signals associated with the transactions between said common control means and said memory means; and F. said common control means further including: ii. first queing means (70) interposed between said transmitting means and said memory bus means for receiving said address, writing control and data signals and for subsequently transmitting said signals to said memory bus means; iii. duplicate tag storage means (86) connected to said cache memory means for maintaining copies of the tag address information stored in the tag portion of said cache memory means; and iv. second queing means (80) connected to said duplicate tag storage means and being interposed between said memory bus means and said receiving means for receiving on a first-in-first out basis said address, memory control and data signals from said main memory means, said second queing means being operative to subsequently transmit to said receiving means said address, memory control, and data signals when said address signal matches an address contained in said duplicate tag storage means thereby to enable said updating means to write the data portion of said cache memory means.
Claim 3
Dependent Claim
83 words
A multiprocessor system as recited in claim 1 wherein said duplicate tag storage means comprises: (a) monitoring means connected to the entry of the second queing means for detecting all read transactions scheduled to allocate said cache memory means, and (b) address signal receiving means for storing said main memory addresses when said read transaction is received by said second queing means thereby to effect changes in the duplicate tag storage means prior to changing the tag portion of said cache memory means.
Claim 4
Dependent Claim
53 words
A multiprocessor system as recited in claims 1 or 2 wherein said common control means includes means connected to said second queing means and said updating means for foregoing an updating operation when said cache memory means is scheduled to be allocated by reading transactions that is queued in said second queing means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-09-13 | 1986-03-15 | 1986-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-09-13 | 1990-03-15 | 1990-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-09-13 | 1994-03-15 | 1994-09-14 | $7700.00 | Window Closed / Lapsed |