Priority encoder

Claim 2

A priority encoder register for receiving a plurality of binary input signals and generating output signals in accordance with a prescribed priority sequence, comprising: a plurality of input means, each coupled to receive one of said binary input signals; a plurality of output means, each coupled to an associated one of said input means and to adjacent ones of said output means, each for generating an output signal if its associated input means has received an input signal of a first logic level; and first means coupled to each of said plurality of output means for blocking all but one of said output signals at a time, said one of said output signals being associated with one of said output means of higher priority, each of said output signals resetting its associated input means to a second logic level to enable another one of said output means of a next lower priority.

Claim 3

A priority encoder register according to claim 1 further including second means for monitoring each of said plurality of input means and for indicating when all of said input means contain said second logic level.

Claim 4

A priority encoder register according to claim 1 wherein each of said input means comprises: a storage latch; third means for loading said storage latch with said input signal during a first time interval; and fourth means coupled to said storage latch and responsive to said output signal for resetting said storage latch.

Claim 5

A priority encoder register according to claim 3 wherein each of said output means comprises logic means having at least a first input coupled to the output of its associated storage means and having an output which is coupled to said fourth means.

Claim 6

A priority encoder register according to claim 4 wherein all but the first of said output means is equipped with a disabling input which is coupled to said first means.

Claim 7

A priority encoder register according to claim 5 wherein said blocking means comprises: means coupled to said disabling input for charging said disabling input to a voltage level which will cause said logic means to be disabled; and means for discharging said disabling input if all previous input means contain a second logic level.

Claim 8

A priority encoder register according to claim 6 wherein said second means comprises: a plurality of field effect transistors, each one coupled to the output of its associated latch, each of said plurality of field effect transistors having a gate coupled to the output of its associated latch, a source coupled to ground and a drain coupled to the drains of each of the others of said plurality of field-effect-transistors; and means for pulling the common drains of each of said plurality of field-effect-transistors high when all of said plurality of field effect transistors are turned off.

Claim 9

A priority encoder register for receiving a plurality of binary input signals and generating therefrom output signals in accordance with the prescribed sequence of priority, comprising: a plurality of storage means, each for storing one of said input signals; a plurality of output means, each one coupled to one of said plurality of storage means and to adjacent ones of said plurality of output means for generating an output indicative of the contents of its associated storage means; first means for forcing all but one of said plurality of output means to a first logic level, said one being the first in said prescribed sequence of priority to be associated with one of said plurality of storage means containing a second logic level; and second means for resetting the storage means associated with said first in said prescribed sequence of priority for forcing all but another one of said plurality of output means to a first logic level, said another one of said output means being the next in said prescribed sequence of priority to be associated with one of said storage means containing said second logic level.

Claim 10

A priority encoder register for receiving a plurality of binary input signals and generating therefrom output signals in accordance with the prescribed sequence of priority, comprising: a plurality of storage means, each for storing one of said input signals; a plurality of output means, each one coupled to one of said plurality of storage means and to adjacent ones of said plurality of output means for generating an output indicative of the contents of its associated storage means; first means for forcing all but one of said plurality of output means to a first logic level, said one being the first in said prescribed sequence of priority to be associated with one of said plurality of storage means containing a second logic level; and second means for resetting the storage means associated with said first in said prescribed sequence of priority for forcing all but another one of said plurality of output means to a first logic level, said another one of said output means being the next in said prescribed sequence of priority to be associated with one of said storage means containing said second logic level.

Claim 11

A priority encoder register according to claim 8 further including third means for monitoring each of said plurality of storage means and for indicating when all of said storage means contain said first logic level.

Claim 12

A priority encoder register according to claim 8 wherein each of said output means comprises logic means having at least a first input coupled to the output of its associated storage means and having an output which is coupled to said second means.

Claim 13

A priority encoder register according to claim 10 wherein all but the first of said output means is equipped with a disabling input which is coupled to said first means.

Claim 14

A priority encoder register according to claim 11 wherein said first means comprises: means coupled to said disabling input for charging said disabling input to a voltage level which will cause said logic means to be blocked; and means for discharging said disabling input if all previous ones of said plurality of storage means contain said first logic level.

Claim 15

A priority and coder register according to claim 12 wherein said third means comprises: a plurality of field-effect-transistors, each one coupled to the output of its associated storage means, each of said plurality of field-effect-transistors having a gate electrode coupled to the output of its associated storage means, a source coupled to ground and a drain coupled to the drains of each of the others of said plurality of field-effect-transistors; and means for pulling the drain electrodes of each of said plurality of field-effect-transitors high when all of said plurality of field-effect-transistors are turned off.

Claim 16

A priority encoder for receiving a plurality of binary input signals each representing the contents of individual bits in a binary data word, said encoder for generating a unique binary code for each bit in said binary data word representing a first logic level in accordance with a prescribed priority sequence, comprising: a plurality of input means, each coupled to receive one said binary input signals; a plurality of output means, each coupled to an associated one of said input means and to adjacent ones of said output means, each for generating an output signal if its associated input means has received an input signal of a first logic level; first means coupled to each of said plurality of output means for blocking all but one of said output signals at a time, said one of said output signal being associated with one of said output means of higher priority, each of said output signals resetting its associated input means to a second logic level enabling another one of said output means of a next lower priority; and encoding means coupled to said plurality of output means for generating a unique binary code in response to receipt of each of said output signals.

Claim 17

A priority encoder for receiving a plurality of binary input signals each representing the contents of individual bits in a binary data word, said encoder for generating a unique binary code for each bit in said binary data word representing a first logic level in accordance with a prescribed priority sequence, comprising: a plurality of input means, each coupled to receive one said binary input signals; a plurality of output means, each coupled to an associated one of said input means and to adjacent ones of said output means, each for generating an output signal if its associated input means has received an input signal of a first logic level; first means coupled to each of said plurality of output means for blocking all but one of said output signals at a time, said one of said output signal being associated with one of said output means of higher priority, each of said output signals resetting its associated input means to a second logic level enabling another one of said output means of a next lower priority; and encoding means coupled to said plurality of output means for generating a unique binary code in response to receipt of each of said output signals.

Claim 18

A priority according to claim 14 further including second means for monitoring each of said plurality of input means and for indicating when all of said input means contains said second logic level.