Control store test selection logic for a data processing system

Claim 2

A data processing system comprising: means for receiving a plurality of test signals, each of said test signals having either a first polarity or a second polarity indicative of the status of various elements included in said system, and for generating a plurality of selected output signals comprising selected ones of said received test signals; first multiplexer means having a plurality of first multiplexer inputs and a first selector enable terminal, said first multiplexer means for generating a first multiplexer output; second multiplexer means having a plurality of second multiplexer inputs and a second selection enable terminal, each of said second multiplexer inputs corresponding to a different one of said plurality of first multiplexer inputs, said second multiplexer means for generating a second multiplexer output; first means for coupling each of said plurality of selected output signals from said receiving and generating means to a different one of said first multiplexer inputs and corresponding second multiplexer inputs; a control store having a first part and a second part, said first part of said control store having a first plurality of addressable storage locations for storing control store words and a first address enable terminal, said second part of said control store having a second plurality of addressable storage locations for storing control store words and a second address enable terminal, said control store words for use in controlling the operation of said system; second means for coupling the output of said first multiplexer means to said first address enable terminal and for coupling the output of said second multiplexer means to said second address enable terminal; and third means for coupling one of said test signals to said first selection enable terminal and to said second selection enable terminal to control said first multiplexer means to generate said first multiplexer output responsive to said one test signal having said first polarity and to control said second multiplexer means to generate said second multiplexer output responsive to said one test signal having said second polarity.

Claim 3

A system as in claim 1 wherein said receiving and generating means comprises a plurality of multiplexer circuits, each of said multiplexer circuits having a plurality of input terminals for selectively receiving said test signals and an output terminal for supplying a different one of said selected output signals.

Claim 4

A system as in claim 2 wherein each of said first multiplexer means and second multiplexer means includes an assertion output terminal and a negation output terminal, said assertion output terminal of said first multiplexer means being coupled to said negation output terminal of said second multiplexer means and being coupled to said first address enable terminal by said second coupling means, said negation output terminal of said first multiplexer means being coupled with said assertion output terminal of said second multiplexer means and being supplied to said second address enable terminal by said second coupling means.

Claim 5

In a data processing system wherein a processor executes a series of microinstructions to perform selected functions and in the course of executing each microinstruction generates an address of a next microinstruction to be executed, a microinstruction storage and retrieval apparatus comprising: a control store having a first part and a second part, said first part of said control store having a first plurality of addressable storage locations for storing microinstructions and a first address enable terminal, said second part of said control store having a second plurality of addressable storage locations for storing microinstructions and a second address enable terminal; means for receiving a plurality of test signals, each of said test signals having either a first polarity or a second polarity indicative of the status of various elements included in said system, and for generating a plurality of selected output signals comprising selected ones of said received test signals; first multiplexer means having a plurality of first multiplexer inputs and a first selection enable terminal, said first multiplexer means for generating a first multiplexer output corresponding to a selected first multiplexer input; second multiplexer means having a plurality of second multiplexer inputs, and a second selection enable terminal, each of said second multiplexer inputs corresponding to a different one of said first multiplexer inputs, said second multiplexer means for generating a second multiplexer output corresponding to one of said second multiplexer inputs; first means for coupling each of said plurality of test signals to a different one of said first multiplexer inputs of said first multiplexer means and to said corresponding second multiplexer input of said second multiplexer means; second means for coupling the output of said first multiplexer means to said first address enable terminal and for coupling the output of said second multiplexer means to said second address enable terminal; and third means for coupling one of said test signals to said first selection enable terminal and to said second selection enable terminal to control said first multiplexer means to generate said first output responsive to said one test signal having said first polarity and to control said second multiplexer means to generate said second output responsive to said one test signal having said second polarity.

Claim 6

In a data processing system wherein a processor executes a series of microinstructions to perform selected functions and in the course of executing each microinstruction generates an address of a next microinstruction to be executed, a microinstruction storage and retrieval apparatus comprising: a control store having a first part and a second part, said first part of said control store having a first plurality of addressable storage locations for storing microinstructions and a first address enable terminal, said second part of said control store having a second plurality of addressable storage locations for storing microinstructions and a second address enable terminal; means for receiving a plurality of test signals, each of said test signals having either a first polarity or a second polarity indicative of the status of various elements included in said system, and for generating a plurality of selected output signals comprising selected ones of said received test signals; first multiplexer means having a plurality of first multiplexer inputs and a first selection enable terminal, said first multiplexer means for generating a first multiplexer output corresponding to a selected first multiplexer input; second multiplexer means having a plurality of second multiplexer inputs, and a second selection enable terminal, each of said second multiplexer inputs corresponding to a different one of said first multiplexer inputs, said second multiplexer means for generating a second multiplexer output corresponding to one of said second multiplexer inputs; first means for coupling each of said plurality of test signals to a different one of said first multiplexer inputs of said first multiplexer means and to said corresponding second multiplexer input of said second multiplexer means; second means for coupling the output of said first multiplexer means to said first address enable terminal and for coupling the output of said second multiplexer means to said second address enable terminal; and third means for coupling one of said test signals to said first selection enable terminal and to said second selection enable terminal to control said first multiplexer means to generate said first output responsive to said one test signal having said first polarity and to control said second multiplexer means to generate said second output responsive to said one test signal having said second polarity.

Claim 7

A microinstruction storage and retrieval apparatus according to claim 4 wherein said first part and said second part of said control store comprise read only memories.

Claim 8

A system as in claim 5 wherein said receiving and generating means comprises a plurality of multiplexer circuits, each of said multiplexer circuits having a plurality of input terminals for selectively receiving said test signals and an output terminal for supplying a different one of said selected output signals.