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US4346473A
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Error correction coding method and apparatus for multilevel signaling
Assignee: Harris Corp
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Filing: 1980-02-26
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Granted: 1982-08-24
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Expires: 2000-02-26
Abstract
Abstract In typical error correction coding techniques for use in multilevel signalling schemes, such as M-level QAM signalling, the full data stream is encoded. In order to eliminate the need for such extensive coding while still allowing for accurate decisions as to the received data, the present system and method provide techniques for only encoding the lower significance bits of the multi-bit signal. The more significant bits are left uncoded. Accurate decisions are still possible in the majority of cases with this technique inasmuch as the most likely errors in uncoded transmission occur in deciding between adjacent received signal levels. These errors are eliminated by encoding the lower significance bits without the need for encoding the more significant bits.
Inventors
- 👤 Robert C. Davis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 14:07
CPC Classifications
H; H04; H04N; H04N21/00; H04N21/40; H04N21/43; H04N21/438; H04N21/4382; H04L; H04L1/00; H04L1/004; H04L1/0056; H04L1/0059; H04L1/006; H04L27/00; H04L27/32; H04L27/34; H04L27/3405; H04L27/3416; H04L27/3427; H04N21/20; H04N21/23; H04N21/238; H04N21/2383
Claims Analysis
Total Claims: 48
Claim 1
Independent Claim
64 words
An error coding system for use in multilevel digital signalling systems comprising: means for providing a multi-bit signal having a most significant bit and at least one lower significance bit; and means for coding at least one of said lower significance bits without encoding the most significant bit of the multi-bit signal to provide an error coded signal for transmission to a receiving station.
Claim 2
Dependent Claim
64 words
An error coding system for use in multilevel digital signalling systems comprising: means for providing a multi-bit signal having a most significant bit and at least one lower significance bit; and means for coding at least one of said lower significance bits without encoding the most significant bit of the multi-bit signal to provide an error coded signal for transmission to a receiving station.
Claim 3
Dependent Claim
37 words
A system according to claim 1, wherein the coding is used for error correction coding so that the transmitted signal is an error correction coded signal which allows correction of any errors detected at the receiving station.
Claim 4
Dependent Claim
14 words
A system according to claim 2, wherein only a least significant bit is coded.
Claim 5
Dependent Claim
25 words
A system according to claim 2, wherein the multi-bit signal includes at least three bits and wherein only the two least significant bits are encoded.
Claim 6
Dependent Claim
97 words
A system according to claim 3, wherein the transmitted error correction coded signal is transmitted with a voltage level representative of the value of the multi-bit signal, the system further comprising: means in said receiving station to receive the error correction coded signal; means for limiting the decision of the actual transmitted level of the error correction coded signal to a choice of two adjacent levels; and means for selecting which of the two adjacent levels of the received signal represents the actual transmitted level based on an evaluation of the coding of the least significant bit.
Claim 7
Dependent Claim
98 words
A system according to claim 4, wherein the transmitted error correction coded signal is transmitted with a voltage level representative of the value of the multi-bit signal, the system further comprising: means in said receiving station to receive the error correction coded signal; means for limiting the decision of the actual transmitted level of the error correction coded signal to a choice of four adjacent levels; and means for selecting which of the four adjacent levels of the received signal represents the actual transmitted level based on an evaluation of the coding of the two least significant bits.
Claim 8
Dependent Claim
20 words
A system according to claim 2, wherein the error correction coded signal is transmitted as a pulse amplitude modulated signal.
Claim 9
Dependent Claim
20 words
A system according to claim 2, wherein the error correction coded signal is transmitted as a quadrature amplitude modulated signal.
Claim 10
Dependent Claim
38 words
A system according to claim 2, wherein the multi-bit signal is a three bit signal, and the transmitted error correction coded signal is one of eight possible voltage levels representative of the values of the three bit signal.
Claim 11
Dependent Claim
17 words
A system according to claim 2, further comprising a convolution coder for coding said lower significance bit.
Claim 12
Dependent Claim
16 words
A system according to claim 10, wherein said convolution coder is a 1/2 rate convolution coder.
Claim 13
Dependent Claim
44 words
A system according to claim 3, wherein the multi-bit signal is a three bit signal and the system further comprises a 1/2 rate convolution coder for coding the least significant bit such that the overall code rate for the three bit signal is 5/6.
Claim 14
Dependent Claim
41 words
A system according to claim 4, wherein the multi-bit signal is a three bit signal, and the system further comprises a 1/2 rate convolution coder for coding the two least significant bits so that the overall signal code rate is 2/3.
Claim 15
Dependent Claim
22 words
A system according to claim 10, wherein the receiving station includes a soft decision Viterbi decoder for decoding the convolution coded signal.
Claim 16
Dependent Claim
23 words
A system according to claim 3, wherein the transmitted encoded signal is an eight level quadrature amplitude modulated signal transmitted at 3.8 bits/sec/Hz.
Claim 17
Dependent Claim
23 words
A system according to claim 4, wherein the transmitted encoded signal is an eight level quadrature amplitude modulated signal transmitted at 3 bits/sec/Hz.
Claim 18
Dependent Claim
90 words
A system according to claim 1, 2 or 6, wherein the means for encoding the lower significance bits comprise means for converting each received lower significance bit into a pair of code branch bits T 1 and T 2 , and further comprising means for using each code branch bit pair to select one of a group of baseband voltages for transmission to the receiver station, wherein a plurality of the transmitted baseband voltages produce a code path, and wherein the minimum distance between any two code paths is: ##EQU9##
Claim 19
Dependent Claim
27 words
A system according to claim 17, wherein the code branch bits T 1 and T 2 select baseband voltages for transmission according to the following relationships: ##EQU10##
Claim 20
Dependent Claim
78 words
A system according to claim 17, wherein the means for encoding further comprises: a shift register for receiving each lower significance bit; a first modulo-2 adder coupled to a first set of stages of the shift register to produce the code branch bit T 1 ; and a second modulo-2 adder coupled to a second set of stages of the shift register different than the first set of stages to produce the code branch bit T 2 .
Claim 21
Independent Claim
111 words
A system for encoding an information bit stream having a most significant bit and at least one lower significant bit for transmission over a transmission channel to a receiving station, comprising: means for converting at least one of said lower significant bits in the bit stream into a pair of code branch bits T 1 and T 2 without encoding the most significant bit; means for using each code branch bit pair to select one of a group of baseband voltages for transmission to the receiving station, wherein a plurality of the transmitted baseband voltages produce a code path, and wherein the minimum distance between any two code paths is: ##EQU11##
Claim 22
Independent Claim
111 words
A system for encoding an information bit stream having a most significant bit and at least one lower significant bit for transmission over a transmission channel to a receiving station, comprising: means for converting at least one of said lower significant bits in the bit stream into a pair of code branch bits T 1 and T 2 without encoding the most significant bit; means for using each code branch bit pair to select one of a group of baseband voltages for transmission to the receiving station, wherein a plurality of the transmitted baseband voltages produce a code path, and wherein the minimum distance between any two code paths is: ##EQU11##
Claim 23
Dependent Claim
27 words
A system according to claim 20, wherein the code branch bits T 1 and T 2 select baseband voltages for transmission according to the following relationships: ##EQU12##
Claim 24
Dependent Claim
78 words
A system according to claim 20, wherein the means for encoding further comprises: a shift register for receiving each lower significance bit; a first modulo-2 adder coupled to a first set of stages of the shift register to produce the code branch bit T 1 ; and a second modulo-2 adder coupled to a second set of stages of the shift register different than the first set of stages to produce the code branch bit T 2 .
Claim 25
Dependent Claim
61 words
An error coding method for use in a multilevel digital signalling system comprising: providing a multi-bit signal having a most significant bit and at least one lower significance bit; and coding at least one of said lower significance bits without encoding the most significant bit in the multi-bit signal to provide an error coded signal for transmission to a receiving station.
Claim 26
Dependent Claim
61 words
An error coding method for use in a multilevel digital signalling system comprising: providing a multi-bit signal having a most significant bit and at least one lower significance bit; and coding at least one of said lower significance bits without encoding the most significant bit in the multi-bit signal to provide an error coded signal for transmission to a receiving station.
Claim 27
Dependent Claim
39 words
A method according to claim 23, wherein the coding is used for error correction coding so that the transmitted signal is an error correction coded signal permitting the receiving station to correct any errors detected in the received signal.
Claim 28
Dependent Claim
14 words
A method according to claim 24, wherein only a least significant bit is encoded.
Claim 29
Dependent Claim
25 words
A method according to claim 24, wherein the multi-bit signal includes at least three bits, and wherein only the two least significant bits are encoded.
Claim 30
Dependent Claim
91 words
A method according to claim 25, wherein the transmitted error correction coded signal is transmitted with a voltage level representative of the value of the multi-bit signal, the method further comprising: receiving the error correction coded signal at the receiving station; limiting the decision of the actual transmitted level of the error correction coded signal to a choice of two adjacent levels; and selecting which of the two adjacent levels of the received signal represents the actual transmitted level based on an evaluation of the coding of the least significant bit.
Claim 31
Dependent Claim
91 words
A method according to claim 26, wherein the transmitted error coded signal is transmitted with a voltage level representative of the value of the multi-bit signal, the method further comprising: receiving the error correction coded signal at the receiving station; limiting the decision of the actual transmitted level of the error correction coded signal to a choice of four adjacent levels, and selecting which of the four adjacent levels of the received signal represents the actual transmitted level based on an evaluation of the coding of the two least significant bits.
Claim 32
Dependent Claim
20 words
A method according to claim 24, wherein the error correction coded signal is transmitted as a pulse amplitude modulated signal.
Claim 33
Dependent Claim
20 words
A method according to claim 24, wherein the error correction coded signal is transmitted as a quadrature amplitude modulated signal.
Claim 34
Dependent Claim
38 words
A method according to claim 24, wherein the multi-bit signal is a three bit signal and the transmitted error correction coded signal is one of eight possible voltage levels representative of the value of the three bit signal.
Claim 35
Dependent Claim
19 words
A method according to claim 24, wherein the coding of said lower significance bit is performed by convolution coding.
Claim 36
Dependent Claim
15 words
A method according to claim 32, wherein the convolution coding is 1/2 rate convolution coding.
Claim 37
Dependent Claim
39 words
A method according to claim 25, wherein the multi-bit signal is a three bit signal and the system further comprises a 1/2 rate convolution coder for coding the least significant bit so that the overall code rate is 5/6.
Claim 38
Dependent Claim
40 words
A method according to claim 26, wherein the multi-bit signal is a three bit signal and the system further comprises a 1/2 rate convolution coder for coding the two least significant bits such that the overall code rate is 2/3.
Claim 39
Dependent Claim
23 words
A method according to claim 32, further comprising using a Viterbi decoding arrangement at the receiving station for decoding the convolution coded signal.
Claim 40
Dependent Claim
24 words
A method according to claim 25, wherein the transmitted correction coded signal is an eight level quadrature amplitude modulated signal transmitted at 3.8 bits/sec/Hz.
Claim 41
Dependent Claim
25 words
A method according to claim 26, wherein the transmitted error correction coded signal is an eight level quadrature amplitude modulated signal transmitted at 3 bits/sec/Hz.
Claim 42
Dependent Claim
83 words
A method according to claim 23, 24, or 28, wherein the step of encoding the lower significance bits comprises converting each lower significance bit into a pair of code branch bits T 1 and T 2 , and further comprising using each code branch bit pair to select one of a group of baseband voltages for transmission to the receiving station, wherein a plurality of transmitted baseband voltages produce a code path, and wherein the minimum distance between any two paths is: ##EQU13##
Claim 43
Dependent Claim
27 words
A method according to claim 39, wherein the code branch bits T 1 and T 2 select baseband voltages for transmission according to the following relationships: ##EQU14##
Claim 44
Dependent Claim
66 words
A method according to claim 39, further comprising: inserting each lower significance bit into a shift register; modulo-2 adding a first set of stages of the shift register to produce the code branch bit T 1 ; and modulo-2 adding of a second set of stages of the shift register different than the first set of stages to produce the code branch bit T 2 .
Claim 45
Independent Claim
103 words
A method for encoding an information bit stream having a most significant bit and at least one lower significant bit for tramsmission over a transmission channel to a receiving station comprising: converting at least one of said lower significant bits into a pair of code branch bits T 1 and T 2 without encoding the most significant bit; using each code branch bit pair to select one of a group of baseband voltages for transmission to the receiving station, wherein a plurality of the transmitted baseband voltages produce a code path, and wherein the minimum distance between any two code paths is: ##EQU15##
Claim 46
Independent Claim
103 words
A method for encoding an information bit stream having a most significant bit and at least one lower significant bit for tramsmission over a transmission channel to a receiving station comprising: converting at least one of said lower significant bits into a pair of code branch bits T 1 and T 2 without encoding the most significant bit; using each code branch bit pair to select one of a group of baseband voltages for transmission to the receiving station, wherein a plurality of the transmitted baseband voltages produce a code path, and wherein the minimum distance between any two code paths is: ##EQU15##
Claim 47
Dependent Claim
27 words
A method according to claim 42, wherein the code branch bits T 1 and T 2 select baseband voltages for transmission according to the following relationships: ##EQU16##
Claim 48
Dependent Claim
66 words
A method according to claim 42, further comprising: inserting each lower significance bit into a shift register; modulo-2 adding a first set of stages of the shift register to produce the code branch bit T 1 ; and modulo-2 adding of a second set of stages of the shift register different than the first set of stages to produce the code branch bit T 2 .
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-08-23 | 1986-02-22 | 1986-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-08-23 | 1990-02-22 | 1990-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-08-23 | 1994-02-22 | 1994-08-24 | $7700.00 | Window Closed / Lapsed |