US4344188A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Balanced modulator
Assignee: Panasonic Holdings Corp
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Filing: 1980-10-09
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Granted: 1982-08-10
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Expires: 2000-10-09
Abstract
Abstract A balanced modulator for use at the mixer stage of the front end of a signal receiver. The modulator has a transistor balanced modulation circuit of the double balanced type having a plurality of emitter coupled transistor pairs, a circuit for increasing the bias current in the balanced modulation circuit corresponding to an increase in the input signal level, and a circuit for reducing the local oscillation signal applied to the balanced modulation circuit corresponding to an increase in the input signal level so that distortion in the balanced modulation circuit is reduced over a wide range of the level of the input signal.
Inventors
- 👤 Kenzo Tanabe
- 👤 Junji Suzuki
- 👤 Masashi Kanno
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 13:43
CPC Classifications
H; H03; H03C; H03C1/00; H03C1/52; H03C1/54; H03D; H03D7/00; H03D7/14; H03D7/1408; H03D7/1425; H03D7/1433; H03D7/145; H03D7/1458; H03D7/1491; H03D2200/00; H03D2200/0001; H03D2200/0033; H03D2200/0041; H03D2200/0043
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
90 words
A balanced modulator characterized in that said modulator is provided with a transistor balanced modulation circuit of a double balanced type using a plurality of emitter coupled transistor pairs, means for increasing bias current in said balanced modulation circuit correspondingly to an increase in an input signal level, and means for reducing local oscillation signal applied to said balanced modulation circuit, correspondingly to an increase in the input signal level, so that distortion in said balanced modulation circuit may be reduced throughout a wide range of said input signal level.
Claim 2
Dependent Claim
90 words
A balanced modulator characterized in that said modulator is provided with a transistor balanced modulation circuit of a double balanced type using a plurality of emitter coupled transistor pairs, means for increasing bias current in said balanced modulation circuit correspondingly to an increase in an input signal level, and means for reducing local oscillation signal applied to said balanced modulation circuit, correspondingly to an increase in the input signal level, so that distortion in said balanced modulation circuit may be reduced throughout a wide range of said input signal level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-08-09 | 1986-02-08 | 1986-08-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-08-09 | 1990-02-08 | 1990-08-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-08-09 | 1994-02-08 | 1994-08-10 | $7700.00 | Window Closed / Lapsed |