Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
478 words
A bipolar mark-space analogue-to-digital converter having balanced scale factors for positive and negative applied voltages comprising: integrating means for receiving an analog input signal to be converted; means for superimposing a periodic signal on the output signal produced by the integrating means; first and second reference signal sources of opposite polarity; first and second level detectors connected to compare the output signal from the integrating means with first and second detector levels respectively, wherein, to balance scale factors substantially independently of drift or imbalance in said reference signal sources, for zero input signal, the periodic signal causes the magnitude of the output signal from the integrating means to exceed the first level by crossing it in a direction away from the second level for at least a substantial fraction of one half of each cycle of the periodic signal, and to fall below the second level by crossing it in a direction away from the first level for at least a substantial fraction of the other half of each cycle of the periodic signal, and wherein analogue input signals of one polarity cause the magnitude of the output signal to exceed the first level for more than said fraction of said one half of each cycle, while analogue input signals of the other polarity cause the magnitude of the output signal to fall below the second level for more than said fraction of said other half of each cycle, the first and second level detectors being arranged to produce first and second control signals respectively when the magnitude of the output signal from the integrating means exceeds the first level and falls below the second level respectively; switch means responsive to the first control signal to apply one of said reference signal sources, opposite in polarity to said one polarity of the analogue input signal to the integrating means, said switch means being also responsive to the second control signal to apply the other of said reference signal sources to the integrating means; means for defining a conversion interval equal in duration to the duration of an integral number of cycles of said periodic signal; further switch means for applying said analogue input signal to the integrating means for the duration of one conversion interval and for applying zero input signal to the integrating means for the duration of another conversion interval; a source of clock pulses; and counter means responsive to the first and second control signals for counting the clock pulses during the application of either of the reference signal sources to the integrating means, whereby the count in the counter means at the end of the one conversion interval, combined with the count at the end of the other conversion interval, is a digital representation of the magnitude of the integral of the analogue input signal over the one conversion interval, corrected for zero drift.
Claim 2
Dependent Claim
478 words
A bipolar mark-space analogue-to-digital converter having balanced scale factors for positive and negative applied voltages comprising: integrating means for receiving an analog input signal to be converted; means for superimposing a periodic signal on the output signal produced by the integrating means; first and second reference signal sources of opposite polarity; first and second level detectors connected to compare the output signal from the integrating means with first and second detector levels respectively, wherein, to balance scale factors substantially independently of drift or imbalance in said reference signal sources, for zero input signal, the periodic signal causes the magnitude of the output signal from the integrating means to exceed the first level by crossing it in a direction away from the second level for at least a substantial fraction of one half of each cycle of the periodic signal, and to fall below the second level by crossing it in a direction away from the first level for at least a substantial fraction of the other half of each cycle of the periodic signal, and wherein analogue input signals of one polarity cause the magnitude of the output signal to exceed the first level for more than said fraction of said one half of each cycle, while analogue input signals of the other polarity cause the magnitude of the output signal to fall below the second level for more than said fraction of said other half of each cycle, the first and second level detectors being arranged to produce first and second control signals respectively when the magnitude of the output signal from the integrating means exceeds the first level and falls below the second level respectively; switch means responsive to the first control signal to apply one of said reference signal sources, opposite in polarity to said one polarity of the analogue input signal to the integrating means, said switch means being also responsive to the second control signal to apply the other of said reference signal sources to the integrating means; means for defining a conversion interval equal in duration to the duration of an integral number of cycles of said periodic signal; further switch means for applying said analogue input signal to the integrating means for the duration of one conversion interval and for applying zero input signal to the integrating means for the duration of another conversion interval; a source of clock pulses; and counter means responsive to the first and second control signals for counting the clock pulses during the application of either of the reference signal sources to the integrating means, whereby the count in the counter means at the end of the one conversion interval, combined with the count at the end of the other conversion interval, is a digital representation of the magnitude of the integral of the analogue input signal over the one conversion interval, corrected for zero drift.
Claim 3
Dependent Claim
13 words
A converter according to claim 1, wherein the level detectors comprise respective transistors.
Claim 4
Dependent Claim
49 words
A converter according to claim 1 wherein the counter means comprises a reversible counter, and means for causing the counter initially to count in one direction during the application of the first reference signal source and in the other direction during the application of the second reference signal source.
Claim 5
Dependent Claim
27 words
A converter according to claim 2, wherein at least one of the detector levels is defined by the threshold voltage required to initiate conduction through the transistors.