US4340867A
Expired / Lapsed
US
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Inverter amplifier
Assignee: Verizon Laboratories Inc
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Filing: 1980-11-05
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Granted: 1982-07-20
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Expires: 2000-11-05
Abstract
Abstract An inverter amplifier employing NMOS FET's having a plurality of capacitance coupled inverter amplifier stages arranged in series. A DC bias is provided at the input of each amplifier stage by a DC bias generator of a reference voltage source, an operational amplifier, and a reference inverter arranged in a negative feedback loop. The DC bias generator is applied to the input of each amplifier stage.
Inventors
- 👤 Jun-ichi Sano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:21
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/30; H03F1/301; H03F3/00; H03F3/04; H03F3/16
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
182 words
An amplifier comprising an input connection for receiving input signals; an amplifier field effect transistor having a first conduction path electrode coupled to a source of operating potential and a second conduction path electrode connected to a point of fixed potential; the input connection being coupled to the gate of the amplifier field effect transistor; an output connection coupled to the first conduction path electrode of the amplifier field effect transistor; DC bias generating means for establishing a DC bias at the amplifier input including a reference field effect transistor having a first conduction path electrode coupled to said source of operating potential and a second conduction path electrode connected to said point of fixed potential, an operational amplifier having a first input connected to the first conduction path electrode of the reference field effect transistor, a source of reference potential for producing a reference voltage connected to the second input of said operational amplifier, the output of the operational amplifier being coupled to the gate of the reference field effect transistor and to the gate of the amplifier field effect transistor.
Claim 2
Dependent Claim
182 words
An amplifier comprising an input connection for receiving input signals; an amplifier field effect transistor having a first conduction path electrode coupled to a source of operating potential and a second conduction path electrode connected to a point of fixed potential; the input connection being coupled to the gate of the amplifier field effect transistor; an output connection coupled to the first conduction path electrode of the amplifier field effect transistor; DC bias generating means for establishing a DC bias at the amplifier input including a reference field effect transistor having a first conduction path electrode coupled to said source of operating potential and a second conduction path electrode connected to said point of fixed potential, an operational amplifier having a first input connected to the first conduction path electrode of the reference field effect transistor, a source of reference potential for producing a reference voltage connected to the second input of said operational amplifier, the output of the operational amplifier being coupled to the gate of the reference field effect transistor and to the gate of the amplifier field effect transistor.
Claim 3
Dependent Claim
46 words
An amplifier in accordance with claim 1 including capacitance means connected between said input connection and the gate of the amplifier field effect transistor; and a high impedance means connected between the output of the operational amplifier and the gate of the amplifier field effect transistor.
Claim 4
Dependent Claim
169 words
An inverter amplifier comprising an input connection for receiving input signals; first and second amplifier field effect transistors connected in series between a source of operating potential and a point of fixed potential; the input connection being coupled to the gate of the first amplifier field effect transistor; an output connection coupled to the juncture of the first and second amplifier field effect transistors; DC bias generating means for establishing a DC bias at the inverter amplifier input including first and second reference field effect transistors connected in series between said source of operating potential and said point of fixed potential, an operational amplifier having a first input connected to the juncture of the first and second reference field effect transistors, a source of reference potential for producing a reference voltage connected to the second input of said operational amplifier, the output of the operational amplifier being coupled to the gate of the first reference field effect transistor and to the gate of the first amplifier field effect transistor.
Claim 5
Dependent Claim
169 words
An inverter amplifier comprising an input connection for receiving input signals; first and second amplifier field effect transistors connected in series between a source of operating potential and a point of fixed potential; the input connection being coupled to the gate of the first amplifier field effect transistor; an output connection coupled to the juncture of the first and second amplifier field effect transistors; DC bias generating means for establishing a DC bias at the inverter amplifier input including first and second reference field effect transistors connected in series between said source of operating potential and said point of fixed potential, an operational amplifier having a first input connected to the juncture of the first and second reference field effect transistors, a source of reference potential for producing a reference voltage connected to the second input of said operational amplifier, the output of the operational amplifier being coupled to the gate of the first reference field effect transistor and to the gate of the first amplifier field effect transistor.
Claim 6
Dependent Claim
49 words
An inverter amplifier in accordance with claim 3 including capacitance means connected between said input connection and the gate of the first amplifier field effect transistor; and a high impedance means connected between the output of the operational amplifier and the gate of the first amplifier field effect transistor.
Claim 7
Dependent Claim
56 words
An inverter amplifier in accordance with claim 4 wherein the ratios of the dimensions of the first amplifier field effect transistor to the dimensions of the second amplifier field effect transistor are equal to the ratios of the dimensions of the first reference field effect transistor to the dimensions of the second reference field effect transistor.
Claim 8
Dependent Claim
32 words
An inverter amplifier in accordance with claim 5 wherein all of said field effect transistors and said operational amplifier are fabricated as an integrated circuit in a single body of semiconductor material.
Claim 9
Dependent Claim
56 words
An inverter amplifier in accordance with claim 3 wherein the gate of the second amplifier field effect transistor is connected to the juncture of the first and second amplifier field effect transistors; and the gate of the second reference field effect transistor is connected to the juncture of the first and second reference field effect transistors.
Claim 10
Dependent Claim
44 words
An inverter amplifier in accordance with claim 7 wherein the reference voltage produced by the source of reference potential is equal to one-half of the difference between the potential of the source of operating potential and the potential of the point of fixed potential.
Claim 11
Dependent Claim
54 words
An inverter amplifier in accordance with claim 7 wherein the source of reference potential includes first and second resistance means connected in series between the source of operating potential and the point of fixed potential; the juncture of the first and second resistance means being connected to the second input of the operational amplifier.
Claim 12
Dependent Claim
20 words
An inverter amplifier in accordance with claim 9 wherein said first and second resistance means are of equal resistive value.
Claim 13
Dependent Claim
56 words
An inverter amplifier in accordance with claim 7 wherein the ratios of the dimensions of the first amplifier field effect transistor to the dimensions of the second amplifier field effect transistor are equal to the ratios of the dimensions of the first reference field effect transistor to the dimensions of the second reference field effect transistor.
Claim 14
Dependent Claim
32 words
An inverter amplifier in accordance with claim 11 wherein all of said field effect transistors and said operational amplifier are fabricated as an integrated circuit in a single body of semiconductor material.
Claim 15
Dependent Claim
20 words
An inverter amplifier in accordance with claim 12 wherein said field effect transistors are N channel metaloxide-silicon field effect transistors.
Claim 16
Dependent Claim
46 words
An inverter amplifier in accordance with claim 13 wherein said first amplifier field effect transistor and said first reference field effect transistor are of the enhancement type; and said second amplifier field effect transistor and said second reference field effect transistor are of the depletion type.
Claim 17
Dependent Claim
32 words
An inverter amplifier in accordance with claim 14 wherein the first input of the operational amplifier is the positive input; and the second input of the operational amplifier is the negative input.
Claim 18
Dependent Claim
30 words
An inverter amplifier in accordance with claim 12 including high impedance means connected between the output of the operational amplifier and the gate of the first amplifier field effect transistor.
Claim 19
Dependent Claim
91 words
An inverter amplifier in accordance with claim 16 including third and fourth amplifier field effect transistors connected in series between the source of operating potential and the point of fixed potential; the gate of the fourth amplifier field effect transistor being connected to the junction of the third and fourth amplifier field effect transistors; said output connection being coupled to the gate of the third amplifier field effect transistor; and high impedance means connected between the output of the operational amplifier and the gate of the third amplifier field effect transistor.
Claim 20
Dependent Claim
54 words
An inverter amplifier in accordance with claim 17 including first capacitance means connected between said input connection and the gate of the first amplifier field effect transistor; and second capacitance means connected between the juncture of the first and second amplifier field effect transistors and the gate of the third amplifier field effect transistor.
References Cited (Backward Citations)
JPS5545260A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-07-19 | 1986-01-18 | 1986-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-07-19 | 1990-01-18 | 1990-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-07-19 | 1994-01-18 | 1994-07-20 | $7700.00 | Window Closed / Lapsed |