MOS Integrated test circuit using field effect transistors

Claim 1

An MOS integrated circuit arrangement with field-effect transistors, in which the individual circuit block sections of the integrated circuit arrangement are interconnected by field-effect transistor switches which are switchable by external test signals, and in which each field-effect transistor is connected to a voltage no higher than ground through its substrate connection, characterized in that for testing at least two circuit blocks, an input block (EB1) and an output block (AB1), individually and in combination, at least three parallel field-effect transistor-switch groups are provided, each connecting to a common connection point (9) which is connected to the supply voltage (+UB) by a first field-effect transistor (T1) of the depletion type connected as a load resistor, the field-effect transistor-switch groups each comprising two series-connected field-effect transistors of the enhancement type, said switch groups further comprising: a first group for testing the input block (EB1) and having a second field-effect transistor (T2) connected with its gate connection to the common connection point (9), with its drain connection both to a first external connection point (7) and by a third field-effect transistor (T3) of the depletion type, connected as a load resistor, to the supply voltage (+UB), and with its source connection to the drain connection of a fourth field-effect transistor (T4) whose source connection is connected to ground and whose gate connection is connected to a first control line (5); a second group for connecting and disconnecting the input block (EB1) and the output block (AB1) and having a fifth field-effect transistor (T5) connected with its drain connection to the common connection point (9), with its gate connection to the output (8) of the input block (EB1), and with its source connection to the drain connection of a sixth field-effect transistor (T6) whose source connection is connected to ground and whose gate connection is connected to a second control line (4); a third group for testing the output block (AB1), in which the drain connection of a seventh field-effect transistor (T7) is connected to the common connection point (9), its gate connection is connected to a second external connection point (3), and its source connection is connected to the drain connection of an eighth field-effect transistor (T8) whose source connection is connected to ground and whose gate connection is connected to a third control line (6).